TE28F008S3-150 Intel, TE28F008S3-150 Datasheet - Page 6

• Manufacturer Part Number: TE28F008S3-150
• Manufacturer: Intel

Specifications of TE28F008S3-150

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 150ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

28F004S3/28F008S3/28F016S3
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
the WSM is performing a block erase, program, or
lock-bit
indicates that the WSM is ready for a new
command, block erase is suspended, program is
suspended, or the device is in deep power-down
mode.
6
4-Mbit: A - A
8-Mbit: A - A
16-Mbit: A - A
0
0
0
configuration
18
19
20
,
,
Address
Address
Counter
Buffer
Input
Latch
operation.
Decoder
Decoder
Y
X
Output
RY/BY#-high
Buffer
Figure 1. Block Diagram
16-Mbit: Thirty-Two
64-Kbyte Blocks
8-Mbit: Sixteen
Comparator
4-Mbit: Eight
Y Gating
DQ - DQ
Identifier
Register
Register
Status
Data
0
7
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
When CE# and RP# pins are at V
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized.
1.3
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick), 44-
lead PSOP (Plastic Small Outline Package) and 40-
bump BGA* CSP (28F008S3 and 28F016S3 only).
Pinouts are shown in Figures 2, 3 and 4.
Buffer
Input
Pinout and Pin Description
Write State
Command
Register
Machine
PRELIMINARY
CCR
Program/Erase
Voltage Switch
current is 3 mA.
I/O Logic
V
V
V
CE#
WE#
OE#
RP#
RY/BY#
GND
CC
PHQV
CC
CC
PP
, the
PHEL
) is
)