TE28F800B3BA110 Intel, TE28F800B3BA110 Datasheet - Page 49

• Manufacturer Part Number: TE28F800B3BA110
• Manufacturer: Intel

Specifications of TE28F800B3BA110

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 110ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 18mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

9.0
9.1
9.1.1
9.1.2
Datasheet
Power and Reset Specifications
Power-Up/Down Characteristics
To prevent any condition that may result in a spurious write or erase operation, Intel recommends
that you power-up V
together. Intel also recommends power-up V
powerdown with or slightly before V
If V
applying VCCQ and VPP. Device inputs must not be driven before supply voltage = VCCMin.
Power supply transitions must only occur when RP# is low.
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices because the
system expects to read from the flash memory when it exits reset. If a CPU reset occurs without a
flash memory reset, proper CPU initialization will not occur because the flash memory may be
providing status information instead of array data. Intel recommends connecting RP# to the system
CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when V
both WE# and CE# must be low for a command write, driving either signal to V
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can occur only after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to V
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
V
The CUI latches commands as issued by system software and is not altered by V
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
V
After any program or Block-Erase operation is complete (even after V
V
the flash-memory array is required.
CC
PPLK
CC
CCQ
transitions above V
, V
), the CUI must be reset to read-array mode through the Read Array command if access to
and/or VPP are not connected to the V
PP,
and RP# Transitions
CC
and V
LKO
(Lockout voltage), is read-array mode.
CCQ
together. Conversely, V
CC
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
.
PP
with or slightly after V
CC
supply, then V
IH
, regardless of the state of its control inputs.
CC
CC
and V
voltages are above V
CC
CCQ
must attain V
CC
PP
must power-down
. Conversely, V
transitions down to
IH
PP
CC
will inhibit
or CE#
Min before
LKO
PP
. Because
must
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