LH28F160BJE-TTL90 Sharp Electronics, LH28F160BJE-TTL90 Datasheet - Page 11

• Manufacturer Part Number: LH28F160BJE-TTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BJE-TTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

3.5 Read Identifier Codes
The
manufacturer code, device code, block lock configuration
codes for each block and the permanent lock configuration
code (see Figure 4). Using the manufacturer and device
codes, the system CPU can automatically match the device
with its proper algorithms. The block lock and permanent
lock configuration codes identify locked and unlocked
blocks and permanent lock-bit setting.
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V
V
erase, full chip erase, word/byte write and lock-bit
configuration.
The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and an address within the device. The Word/Byte Write
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
device (Permanent Lock) or block within the device
(Block Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address within the
device.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 16 and 17 illustrate WE# and CE# controlled write
operations.
4 COMMAND DEFINITIONS
When the V
the status register, identifier codes, or blocks are enabled.
Placing V
erase, full chip erase, word/byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these commands.
CCW
=V
read
CCWH1/2
CCWH1/2
CCW
identifier
voltage V
, the CUI additionally controls block
on V
codes
CCW
CCWLK
enables successful block
operation
, read operations from
CC
=2.7V-3.6V and
outputs
the
[A
FDFFF
FCFFF
FFFFF
FEFFF
FD003
FD002
FD001
FD000
EFFFF
F8FFF
F7FFF
FF003
FF002
FF001
FF000
FE003
FE002
FE001
FE000
07FFF
F9000
F8003
F8002
F8001
F8000
F0003
F0002
F0001
F0000
08000
00004
00003
00002
00001
00000
19
Figure 4. Device Identifier Code Memory Map
-A
0
*
]
*
: Address A
Parameter Block 0 Lock Configuration Code
Parameter Block 5 Lock Configuration Code
Main Block 30 Lock Configuration Code
Main Block 0 Lock Configuration Code
Boot Block 0 Lock Configuration Code
Boot Block 1 Lock Configuration Code
Permanent Lock Configuration Code
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
Reserved for Future Implementation
(Parameter Blocks 1 through 4)
(Main Blocks 1 through 29)
Manufacturer Code Main Block 30
-1
don’t care.
Device Code
Top Boot
Parameter Block 0
Parameter Block 5
Main Block 0
Boot Block 0
Boot Block 1
Rev. 1.26