LH28F008BJT-BTLZ1 Sharp Electronics, LH28F008BJT-BTLZ1 Datasheet - Page 15

• Manufacturer Part Number: LH28F008BJT-BTLZ1
• Manufacturer: Sharp Electronics

Specifications of LH28F008BJT-BTLZ1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

4.1 Read Array Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode. This
operation is also initiated by writing the Read Array
command. The device remains enabled for reads until
another command is written. Once the internal WSM has
started a block erase, full chip erase, byte write or lock-bit
configuration the device will not recognize the Read Array
command until the WSM completes its operation unless
the WSM is suspended via an Erase Suspend or Byte
Write Suspend command. The Read Array command
functions independently of the V
be V
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command. Following the command
write, read cycles from addresses shown in Figure 4
retrieve the manufacturer, device, block lock configuration
and permanent lock configuration codes (see Table 4 for
identifier code values). To terminate the operation, write
another valid command. Like the Read Array command,
the
independently of the V
Following the Read Identifier Codes command, the
following information can be read:
NOTE:
1. BA selects the specific block lock configuration code
sharp
Manufacture Code
Device Code
Block Lock Configuration
•Block is Unlocked
•Block is Locked
•Reserved for Future Use
Permanent Lock Configuration
•Device is Unlocked
•Device is Locked
•Reserved for Future Use
to be read. See Figure 4 for the device identifier code
memory map.
IH
Read
.
Code
Identifier
Table 4. Identifier Codes
CCW
Codes
voltage and RP# can be V
CCW
Address
[A
BA
00000H
00001H
00003H
command
19
voltage and RP# can
(1)
-A
+2
0
(2)
]
[DQ
Data
DQ
DQ
DQ
DQ
DQ
DQ
functions
EDH
B0H
7
-DQ
0
0
0
0
1-7
1-7
=0
=1
=0
=1
(3)
IH
0
LHF08JZ1
]
.
4.3 Read Status Register Command
The status register may be read to determine when a block
erase, full chip erase, byte write or lock-bit configuration
is complete and whether the operation completed
successfully. It may be read at any time by writing the
Read Status Register command. After writing this
command, all subsequent read operations output data from
the status register until another valid command is written.
The status register contents are latched on the falling edge
of OE# or CE#, whichever occurs. OE# or CE# must
toggle to V
register latch. The Read Status Register command
functions independently of the V
V
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear Status
Register command. These bits indicate various failure
conditions (see Table 6). By allowing system software to
reset these bits, several operations (such as cumulatively
erasing multiple blocks or writing several bytes in
sequence) may be performed. The status register may be
polled to determine if an error occurred during the
sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently of
the applied V
command is not functional during block erase or byte
write suspend modes.
IH
.
IH
before further reads to update the status
CCW
Voltage. RP# can be V
CCW
voltage. RP# can be
Rev. 1.27
IH
. This
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