LH28F800BGE-TL85 Sharp Electronics, LH28F800BGE-TL85 Datasheet
LH28F800BGE-TL85
Specifications of LH28F800BGE-TL85
Related parts for LH28F800BGE-TL85
LH28F800BGE-TL85 Summary of contents
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... Their enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F800BG-L/BGH-L offer two levels of protection : absolute protection with V PP hardware boot block locking. These alternatives give designers ultimate control of their code security needs ...
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COMPARISON TABLE OPERATING VERSIONS TEMPERATURE LH28F800BG +70°C (FOR TSOP, CSP) LH28F800BGH-L –40 to +85°C (FOR TSOP, CSP) 1 LH28F800BG +70°C (FOR SOP) 1 Refer to the datasheet of LH28F800BG-L (FOR SOP). PIN CONNECTIONS 48-PIN TSOP (Type ...
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BLOCK ORGANIZATION This product features an asymmetrically-blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100 000 times. For the address locations of the blocks, see the memory map in Fig. ...
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... DEVICE POWER SUPPLY : Internal detection configures the device for 2 operation. To switch from one voltage to another, ramp V ramp V V SUPPLY CC attempts to the flash memory are inhibited. Device operations at invalid V (see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should not be attempted. GND SUPPLY GROUND : Do not float any ground pins. ...
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... INTRODUCTION This datasheet contains LH28F800BG-L/BGH-L specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F800BG-L/ BGH-L flash memories documentation also includes ordering information which is referenced in Section 7. 1.1 New Features Key enhancements of LH28F800BG-L/BGH-L SmartVoltage flash memories are : • ...
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... The boot block is located at either the top or the bottom of the address map accommodate different micro-processor protect for boot code location. The hardware-lockable boot block provides complete code security for the kernel code required for system initialization ...
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Top Boot 7FFFF 4 k-Word Boot Block 7F000 7EFFF 4 k-Word Boot Block 7E000 7DFFF 4 k-Word Parameter Block 7D000 7CFFF 4 k-Word Parameter Block 7C000 7BFFF 4 k-Word Parameter Block 7B000 7AFFF 4 k-Word Parameter Block 7A000 79FFF 4 ...
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... BUS OPERATION The local CPU reads and writes flash memory in- system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the V voltage ...
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... IH command can be written. As with any automated device important to LH28F800BG-L/BGH-L (FOR TSOP, CSP) assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase word write modes CPU reset occurs with no ...
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The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high ...
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BUS CYCLES COMMAND REQ Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write Resume NOTES : 1. Bus operations are defined in Table ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
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The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in ...
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... The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear ...
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Table 5 Write Protection Alternatives OPERATION V RP# WP All Blocks Locked. IL Block Erase V X All Blocks Locked All Blocks Unlocked. HH > V PPLK Word Write V 2 Boot ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write 40H or 10H, Address Write Word Data and Address Read Status Register Suspend Word No Write Loop 0 Suspend SR.7 = Word Write Yes 1 Full Status Check if Desired Word Write Complete FULL STATUS CHECK PROCEDURE Read ...
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Start Write B0H Read Status Register 0 SR Block Erase SR.6 = Completed 1 Read Read Word Write or Word Write? Read Array Data Word Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed ...
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Start Write B0H Read Status Register 0 SR Word Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Word Write Resumed Array Data Fig. 6 Word Write ...
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... GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 V Trace on Printed Circuit Boards PP Updating flash memories that reside in the target system requires that the printed circuit board designers pay attention to the V trace. The V pin supplies the memory cell current PP for word writing and block erasing ...
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... When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during . LKO system idle time. Flash memory’s nonvolatility increases usable battery life because data is PP retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied ...
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ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings Operating Temperature • LH28F800BG-L During Read, Block Erase and Word Write ............................. 0 to +70°C Temperature under Bias ............. –10 to +80°C • LH28F800BGH-L During Read, Block Erase and Word Write ........................ –40 ...
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CAPACITANCE SYMBOL PARAMETER C Input Capacitance IN C Output Capacitance OUT NOTE : 1. Sampled, not 100% tested. 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7 V for a Logic ...
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V 1N914 DEVICE UNDER TEST Includes Jig L Capacitance Fig. 10 Transient Equivalent Testing Load Circuit LH28F800BG-L/BGH-L (FOR TSOP, CSP) Test Configuration Capacitance Loading Value TEST CONFIGURATION V = 3.3±0.3 V, ...
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DC CHARACTERISTICS SYMBOL PARAMETER I Input Load Current LI I Output Leakage Current Standby Current CCS CC V Deep Power- LH28F800BG CCD Down Current LH28F800BGH Read Current CCR Word ...
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DC CHARACTERISTICS (contd.) SYMBOL PARAMETER V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL Output High Voltage V OH1 (TTL) Output High Voltage V OH2 (CMOS) V Lockout Voltage during PP V PPLK ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High ...
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Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/Q) (DQ - ...
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AC CHARACTERISTICS - WRITE OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup ...
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AC CHARACTERISTICS - WRITE OPERATIONS (contd.) • 3.3±0 +70˚C or – VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL ...
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AC CHARACTERISTICS - WRITE OPERATIONS (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to WE# t PHWL Going Low t CE# Setup to WE# Going ...
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V IH ADDRESSES ( CE# ( ELWL V IH OE# ( WE# ( High Z DATA (D/ PHWL ...
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ALTERNATIVE CE#-CONTROLLED WRITES • 2 +70˚C or – VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t ...
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ALTERNATIVE CE#-CONTROLLED WRITES (contd.) • 3.3±0 +70˚C or – VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# ...
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ALTERNATIVE CE#-CONTROLLED WRITES (contd.) • 5.0±0.25 V, 5.0±0 VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV RP# High Recovery to CE# t PHEL Going Low t WE# Setup to CE# Going Low WLEL ...
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V IH ADDRESSES ( WE# ( WLEL V IH OE# ( CE# ( High Z DATA (D/ PHEL IL ...
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RESET OPERATIONS V OH RY/BY# ( RP# ( RY/BY# ( RP# ( 2.7 V/3.3 V RP# ...
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BLOCK ERASE AND WORD WRITE PERFORMANCE • 2 +70˚C or – SYMBOL PARAMETER NOTE 32 k-Word t Word Write Block WHQV1 t Time 4 k-Word EHQV1 ...
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BLOCK ERASE AND WORD WRITE PERFORMANCE (contd.) • 5.0 V±0.25 V, 5.0±0 SYMBOL PARAMETER t 32 k-Word Block WHQV1 Word Write Time t 4 k-Word Block EHQV1 32 k-Word Block Block Write Time 4 ...
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... ORDERING INFORMATION Product line designator for all SHARP Flash products (H) E Device Density 800 = 8 M-bit Architecture B = Boot Block Power Supply Type G = SmartVoltage Technology Operating Temperature Blank = – + OPTION ORDER CODE 1.35 V I/O Levels 1 LH28F800BGXX-XL85 2 LH28F800BGXX-XL12 LH28F800BG-L/BGH-L (FOR TSOP, CSP Access Speed (ns ...
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TSOP (TSOP048-P-1220 20.0 0.3 18.4 0.2 Package base plane 0.1 19.0 PACKAGING ...
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CSP (FBGA048-P-0808) 0.1 S 0.8 0 0.1 S TYP. 0 0.2 8 TYP. TYP 1.2 0.03 0. PACKAGING Land hole ...