LH28F800SGE-L10 Sharp Electronics, LH28F800SGE-L10 Datasheet - Page 4

• Manufacturer Part Number: LH28F800SGE-L10
• Manufacturer: Sharp Electronics

Specifications of LH28F800SGE-L10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 19b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 2.7/3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTION
DQ
SYMBOL
RY/BY#
A
RP#
WE#
WP#
GND
CE#
OE#
V
V
0
0
NC
-DQ
-A
CC
PP
18
15
OUTPUT
OUTPUT
SUPPLY
SUPPLY
SUPPLY
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
TYPE
ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses
are internally latched during a write cycle.
DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs
data during memory array, status register, and identifier code read cycles. Data pins
float to high-impedance when the chip is deselected or outputs are disabled. Data is
internally latched during a write cycle.
CHIP ENABLE : Activates the device's control logic, input buffers, decoders, and sense
amplifiers. CE#-high deselects the device and reduces power consumption to standby
levels.
RESET/DEEP POWER-DOWN : Puts the device in deep power-down mode and resets
internal automation. RP#-high enables normal operation. When driven low, RP# inhibits
write operations which provide data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
RP# at V
configuration with V
attempted.
OUTPUT ENABLE : Controls the device's outputs during a read cycle.
WRITE ENABLE : Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
WRITE PROTECT : Master control for block locking. When V
erased and programmed, and block lock-bits can not be set and reset.
READY/BUSY : Indicates the status of the internal WSM. When low, the WSM is
performing an internal operation (block erase, word write, or lock-bit configuration).
RY/BY#-high indicates that the WSM is ready for new commands, block erase is
suspended, and word write is inactive, word write is suspended, or the device is in deep
power-down mode. RY/BY# is always active and does not float when the chip is
deselected or data outputs are disabled.
BLOCK ERASE, WORD WRITE, LOCK-BIT CONFIGURATION POWER SUPPLY :
For erasing array blocks, writing words, or configuring lock-bits. With V
memory contents cannot be altered. Block erase, word write, and lock-bit configuration
with an invalid V
results and should not be attempted.
DEVICE POWER SUPPLY : Internal detection configured the device for 2.7 V, 3.3 V or
5 V operation. To switch from one voltage to another, ramp V
ramp V
attempts to the flash memory are inhibited. Device operations at invalid V
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious results and should
not be attempted.
GROUND : Do not float any ground pins.
NO CONNECT : Lead is not internal connected; recommend to be floated.
CC
HH
to the new voltage. Do not float any power pins. With V
allows to set permanent lock-bit. Block erase, word write, or lock-bit
PP
(see Section 6.2.3 "DC CHARACTERISTICS") produce spurious
IH
< RP# < V
- 4 -
NAME AND FUNCTION
HH
LH28F800SG-L/SGH-L (FOR TSOP, CSP)
produce spurious results and should not be
IL
CC
, locked blocks cannot be
down to GND and then
CC
≤ V
LKO
PP
CC
, all write
≤ V
voltage
PPLK
,