LH28F800BVE-TTL90 Sharp Electronics, LH28F800BVE-TTL90 Datasheet - Page 16

• Manufacturer Part Number: LH28F800BVE-TTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F800BVE-TTL90

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

4.8 Word/Byte Write Suspend Command
The
word/byte write interruption to read data in other flash
memory locations. Once the word/byte write process
starts, writing the Word/Byte Write Suspend command
requests that the WSM suspend the word/byte write
sequence at a predetermined point in the algorithm. The
device continues to output status register data when read
after the Word/Byte Write Suspend command is written.
Polling status register bits SR.7 and SR.2 can determine
when the word/byte write operation has been suspended
(both will be set to "1"). RY/BY# will also transition to
High Z. Specification t
suspend latency.
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while
word/byte write is suspended are Read Status Register and
Word/Byte Write Resume. After Word/Byte Write
Resume command is written to the flash memory, the
WSM will continue the word/byte write process. Status
register bits SR.2 and SR.7 will automatically clear and
RY/BY# will return to V
Resume command is written, the device automatically
outputs status register data when read (see Figure 8). V
must remain at V
word/byte write) while in word/byte write suspend mode.
RP# must also remain at V
used for word/byte write). WP# must also remain at V
V
4.9 Considerations of Suspend
After the suspend command write to the CUI, read status
register command has to write to CUI, then status register
bit SR.6 or SR.2 should be checked for places the device
in suspend mode.
IH
Word/Byte Write
(the same WP# level used for word/byte write).
Block Erase
Operation
Word/Byte
or
PPH1/2
Write
WHRZ1
>V
V
V
OL
(the same V
PPLK
IH
PP
IL
Suspend
. After the Word/Byte Write
or V
defines the word/byte write
HH
V
RP#
(the same RP# level
V
V
X
command
HH
PP
IH
IL
level used for
Table 6. Write Protection Alternatives
WP#
V
V
allows
X
X
X
IH
IL
IL
PP
or
All Blocks Locked.
All Blocks Locked.
All Blocks Unlocked.
2 Boot Blocks Locked.
All Blocks Unlocked.
4.10 Block Locking
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
4.10.1 V
The V
complete write protection of all blocks in the flash device.
4.10.2 WP#=V
The lockable blocks are locked when WP#=V
program or erase operation to a locked block will result in
an error, which will be reflected in the status register. For
top configuration, the top two boot blocks are lockable.
For the bottom configuration, the bottom two boot blocks
are lockable. Unlocked blocks can be programmed or
erased normally (Unless V
4.10.3 WP#=V
WP#=V
These blocks can now be programmed or erased.
WP# controls 2 boot blocks locking and V
protection against spurious writes. Table 6 defines the
write protection methods.
PP
IH
unlocks all lockable blocks.
programming voltage can be held low for
PP
=V
IL
IL
IH
for Complete Protection
for Block Locking
Effect
for Block Unlocking
PP
is below V
PPLK
).
PP
provides
Rev. 1.1
IL
; any