AT49LV4096A-70TC Atmel, AT49LV4096A-70TC Datasheet - Page 3

• Manufacturer Part Number: AT49LV4096A-70TC
• Manufacturer: Atmel

Specifications of AT49LV4096A-70TC

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 3 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 25mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

Block Diagram
Device Operation
1618H–FLASH–4/04
READ: The AT49BV/LV4096A is accessed like an EPROM. When CE and OE are low
and WE is high, the data stored at the memory location determined by the address pins
is asserted on the outputs. The outputs are put in the high-impedance state whenever
CE or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first powered on, it will be reset to the
read or standby mode, depending upon the state of the control line inputs. In order to
perform other device functions, a series of command sequences are entered into the
device. The command sequences are shown in the Command Definitions table (I/O8 -
I/O15 are don’t care inputs for the command codes). The command sequences are writ-
ten by applying a low pulse on the WE or CE input with CE or WE low (respectively) and
OE high. The address is latched on the falling edge of CE or WE, whichever occurs last.
The data is latched by the first rising edge of CE or WE. Standard microprocessor write
timings are used. The address locations used in the command sequences are not
affected by entering the command sequences.
RESET: A RESET input pin is provided to ease some system applications. When
RESET is at a logic high level, the device is in its standard operating mode. A low level
on the RESET input halts the present device operation and puts the outputs of the
device in a high-impedance state. When a high level is reasserted on the RESET pin,
the device returns to the read or standby mode, depending upon the state of the control
inputs. By applying a 12V ± 0.5V input signal to the RESET pin, the boot block array can
be reprogrammed even if the boot block program lockout feature has been enabled (see
“Boot Block Programming Lockout Override” section).
ERASURE: Before a byte or word can be reprogrammed, it must be erased. The erased
state of memory bits is a logic “1”. The entire device can be erased by using the Chip
Erase command or individual sectors can be erased by using the Sector Erase
commands.
ADDRESS
INPUTS
RESET
GND
VCC
WE
OE
CE
Y DECODER
X DECODER
CONTROL
LOGIC
DATA INPUTS/OUTPUTS
PROGRAM DATA
INPUT/OUTPUT
MAIN MEMORY
(240K WORDS)
AT49BV/LV4096A
PARAMETER
PARAMETER
BOOT BLOCK
I/O0 - I/O15
4K WORDS
4K WORDS
BUFFERS
LATCHES
Y-GATING
8K WORDS
BLOCK 2
BLOCK 1
3FFFF
03FFF
02FFF
01FFF
00000
04000
03000
02000
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