M29W400DB55ZE1 Micron Technology Inc, M29W400DB55ZE1 Datasheet
M29W400DB55ZE1
Specifications of M29W400DB55ZE1
Available stocks
Related parts for M29W400DB55ZE1
M29W400DB55ZE1 Summary of contents
Page 1
... RoHS packages Automotive Device Grade 3 – Temperature: –40 to 125 °C – Automotive grade certified April 2009 4 Mbit (512 256 Kb x 16, boot block) 1. These packages are no more in mass production. Rev 8 M29W400DT M29W400DB 3 V supply Flash memory (1) SO44 (M) TSOP48 ( FBGA (1) TFBGA48 (ZA FBGA ...
Page 2
Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.7 Chip Erase ...
Page 4
List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
Description The M29W400D Mbit (512 256 K x 16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (2.7 to 3.6 V) ...
Page 7
Figure 1. Logic diagram A0-A17 Table 1. Signal names Signal name A0-A17 Address inputs DQ0-DQ7 Data inputs/outputs DQ8-DQ14 Data inputs/outputs DQ15A–1 Data input/output or Address input E Chip Enable G Output Enable W Write Enable RP ...
Page 8
Figure 2. SO connections Not connected. 8/ A17 A10 A11 A12 A3 8 ...
Page 9
Figure 3. TSOP connections A15 A14 A13 A12 A11 A10 A17 Not connected A16 BYTE V SS DQ15A–1 ...
Page 10
Figure 4. TFBGA connections (top view through package Not connected. 10/ A17 ...
Page 11
Figure 5. Block addresses (x 8) M29W400DT Top boot block addresses (x 8) 7FFFFh 16 Kbyte 7C000h 7BFFFh 8 Kbyte 7A000h 79FFFh 8 Kbyte 78000h 77FFFh 32 Kbyte 70000h 6FFFFh 64 Kbyte 60000h 1FFFFh 64 Kbyte 10000h 0FFFFh 64 Kbyte ...
Page 12
Figure 6. Block addresses (x 16) M29W400DT Top boot block addresses (x 16) 3FFFFh 8 Kword 3E000h 3DFFFh 4 Kword 3D000h 3CFFFh 4 Kword 3C000h 3BFFFh 16 Kword 38000h 37FFFh 32 Kword 30000h 0FFFFh 32 Kword 08000h 07FFFh 32 Kword ...
Page 13
Signal descriptions See Figure 1: Logic this device. 2.1 Address inputs (A0-A17) The Address inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the ...
Page 14
Write Enable (W) The Write Enable, W, controls the Bus Write operation of the memory’s command interface. 2.8 Reset/Block Temporary Unprotect (RP) The Reset/Block Temporary Unprotect pin can be used to apply a hardware reset to the memory or ...
Page 15
V supply voltage CC The V supply voltage supplies the power for all operations (Read, Program, Erase etc.). CC The command interface is disabled when the V voltage This prevents Bus Write operations from accidentally damaging the ...
Page 16
Bus operations There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See operations, for a summary. Typically glitches of less than Chip Enable ...
Page 17
Special bus operations Additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. These bus operations are intended for use by programming equipment and are not usually used in applications. ...
Page 18
Table 3. Bus operations, BYTE = V Operation Bus Read Bus Write Output Disable Standby Read manufacturer code Read device code 18/48 IH Address inputs A0-A17 V V ...
Page 19
Command interface All Bus Write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the ...
Page 20
During the program operation the memory will ignore all commands not possible to issue any command to abort or pause the operation. Typical program times are given in Table 4: Program, Erase times and Program, Erase endurance during ...
Page 21
No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands not possible to issue any command to abort the operation. ...
Page 22
Program/Erase controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase ...
Page 23
Table 5. Commands, 16-bit mode, BYTE = V Command 1st Addr 1 X Read/Reset 3 555 Auto Select 3 555 Program 4 555 Unlock Bypass 3 555 Unlock Bypass 2 X Program Unlock Bypass 2 X Reset Chip Erase 6 ...
Page 24
Status Register Bus Read operations from any address always read the Status Register during Program and Erase operations also read during Erase Suspend when an address within a block being erased is accessed. The bits in the ...
Page 25
Error bit (DQ5) The Error bit can be used to identify errors detected by the Program/Erase controller. The Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data ...
Page 26
Table 7. Status Register bits Operation Block Erase before timeout Block Erase Erase Suspend Erase Error 1. Unspecified data bits should be ignored. Figure 7. Data polling flowchart 26/48 (1) (continued) Address DQ7 DQ6 Erasing block 0 Toggle Non-erasing 0 ...
Page 27
Figure 8. Data toggle flowchart START READ DQ6 READ DQ5 & DQ6 DQ6 NO = TOGGLE YES NO DQ5 = 1 YES READ DQ6 TWICE DQ6 NO = TOGGLE YES FAIL PASS AI01370C 27/48 ...
Page 28
Maximum rating Stressing the device above the rating listed in cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device ...
Page 29
DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement ...
Page 30
Table 10. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT 1. Sampled only, not 100% tested. Table 11. DC characteristics Symbol I Input Leakage current LI I Output Leakage current LO I Supply current (Read) CC1 I ...
Page 31
Table 12. Read AC characteristics Symbol Alt t t Address Valid to Next Address Valid AVAV Address Valid to Output Valid AVQV ACC ( Chip Enable Low to Output Transition ELQX Chip ...
Page 32
Figure 12. Write AC waveforms, Write Enable controlled A0-A17/ A– DQ0-DQ7/ DQ8-DQ15 V CC tVCHEL RB Table 13. Write AC characteristics, Write Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV WC t ...
Page 33
Figure 13. Write AC waveforms, Chip Enable controlled A0-A17/ A–1 W tWLEL G tGHEL E DQ0-DQ7/ DQ8-DQ15 V CC tVCHWL RB Table 14. Write AC characteristics, Chip Enable controlled Symbol Alt t t Address Valid to Next Address Valid AVAV ...
Page 34
Figure 14. Reset/Block Temporary Unprotect AC waveforms tPLPX RP Table 15. Reset/Block Temporary Unprotect AC characteristics Symbol Alt (1) t PHWL RP High to Write Enable Low, Chip Enable t t PHEL RH Low, Output Enable ...
Page 35
Package mechanical Figure 15. SO44 - 44 lead plastic small outline, 525 mils body width, package outline b 1. Drawing is not to scale. Table 16. SO44 – 44 lead plastic small outline, 525 mils body width, package mechanical ...
Page 36
Figure 16. TSOP48 – 48 lead plastic thin small outline mm, package outline DIE 1. Drawing is not to scale. Table 17. TSOP48 – 48 lead plastic thin small outline mm, ...
Page 37
Figure 17. TFBGA48 mm active ball array, 0.80 mm pitch, bottom view package outline FD FE BALL "A1" Drawing is not to scale. Table 18. TFBGA48 mm, ...
Page 38
Figure 18. TFBGA48 mm active ball array, 0.80 mm pitch, bottom view package outline 1. Drawing is not to scale. Table 19. TFBGA48 mm active ball array, 0.80 ...
Page 39
Part numbering Table 20. Ordering information scheme Example: Device type M29 Operating voltage 2 Device Function 400D = 4 Mbit (512 256 K x 16), boot block ...
Page 40
Appendix A Block address table Table 21. Top boot block addresses M29W400DT # Size (Kbytes Table 22. Bottom ...
Page 41
... Block protection Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. temporary unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP ...
Page 42
Table 23. Programmer technique bus operations, BYTE = V Operation Block Protect Chip Unprotect Block Protection Verify Block Unprotection Verify 42/48 Address inputs A0-A17 A12-A17 block address pulse ...
Page 43
Figure 19. Programmer equipment block protect flowchart ADDRESS = BLOCK ADDRESS START Wait 4 µ Wait 100 µs W ...
Page 44
Figure 20. Programmer equipment chip unprotect flowchart NO 44/48 START PROTECT ALL BLOCKS CURRENT BLOCK = 0 A6, A12, A15 = Wait 4 µ Wait ...
Page 45
Figure 21. In-system equipment block protect flowchart WRITE 60h ADDRESS = BLOCK ADDRESS WRITE 60h ADDRESS = BLOCK ADDRESS ...
Page 46
Figure 22. In-system equipment chip unprotect flowchart 46/48 START PROTECT ALL BLOCKS CURRENT BLOCK = WRITE 60h ANY ADDRESS WITH ...
Page 47
... Revision history moved to end of document. Typical after 100k W/E cycles column removed from 2.0 Erase times and Program, Erase endurance Erase Suspend latency time parameters added. Common Flash interface removed from datasheet. Lead-free package options E and F added to information scheme. ...
Page 48
... Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting Numonyx's website at http://www.numonyx.com. Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. ...