M29W160DB90N1 Micron Technology Inc, M29W160DB90N1 Datasheet - Page 18
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M29W160DB90N1
Manufacturer Part Number
M29W160DB90N1
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M29W160DB90N1.pdf
(42 pages)
Specifications of M29W160DB90N1
Cell Type
NOR
Density
16Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
21/20Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
2M/1M
Supply Current
10mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M29W160DB90N1
Manufacturer:
ST
Quantity:
576
Part Number:
M29W160DB90N1
Manufacturer:
ST
Quantity:
20 000
Company:
Part Number:
M29W160DB90N1/70N6
Manufacturer:
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Quantity:
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M29W160DT, M29W160DB
Bit is set to ’0’ and additional blocks to be erased
may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Al-
ternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations from addresses
within the blocks being erased. A protected block
is treated the same as a block not being erased.
Once the operation completes the memory returns
to Read mode.
Table 7. Status Register Bits
Note: Unspecified data bits should be ignored.
18/42
Program
Program During Erase
Suspend
Program Error
Chip Erase
Block Erase before
timeout
Block Erase
Erase Suspend
Erase Error
Operation
Faulty Block Address
Good Block Address
Non-Erasing Block
Non-Erasing Block
Non-Erasing Block
Erasing Block
Erasing Block
Erasing Block
Any Address
Any Address
Any Address
Any Address
Address
Alternative
DQ7
DQ7
DQ7
DQ7
0
0
0
0
0
1
0
0
During Erase Suspend the Alternative Toggle Bit
changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the
blocks being erased. Bus Read operations to ad-
dresses within blocks not being erased will output
the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit
to be set the Alternative Toggle Bit can be used to
identify which block or blocks have caused the er-
ror. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Opera-
tions from addresses within blocks that have not
erased correctly. The Alternative Toggle Bit does
not change if the addressed block has erased cor-
rectly.
No Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ6
Data read as normal
DQ5
0
0
1
0
0
0
0
0
0
1
1
DQ3
–
–
–
1
0
0
1
1
–
1
1
No Toggle
No Toggle
No Toggle
Toggle
Toggle
Toggle
Toggle
Toggle
DQ2
–
–
–
RB
0
0
0
0
0
0
0
0
1
1
0
0