PA28F800B5B90 Intel, PA28F800B5B90 Datasheet - Page 10

• Manufacturer Part Number: PA28F800B5B90
• Manufacturer: Intel

Specifications of PA28F800B5B90

• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F200B5, 28F004/400B5, 28F800B5
2.3
The
asymmetrically-blocked
system memory integration. Each erase block can
be erased independently of the others up to
100,000 times for commercial temperature or up to
10,000
automotive temperature, each parameter block can
be erased independently 30,000 times, and each
main and boot block 1,000 times. The block sizes
have been chosen to optimize their functionality for
common applications of nonvolatile storage. The
combination of block sizes in the boot block
architecture
memories into a single chip. For the address
locations of the blocks, see the memory maps in
Figures 4, 5, 6 and 7.
2.3.1
The boot block is intended to replace a dedicated
boot PROM in a microprocessor or microcontroller-
based system. The 16-Kbyte (16,384 bytes) boot
block is located at either the top (denoted by -T
suffix) or the bottom (-B suffix) of the address map
to accommodate different microprocessor protocols
for boot code location. This boot block features
hardware controllable write-protection to protect the
crucial microprocessor boot code from accidental
modification. The protection of the boot block is
controlled using a combination of the V
WP# pins, as is detailed in Section 3.3.
10
boot
Memory Blocking Organization
times
ONE 16-KB BOOT BLOCK
block
allow
WE#
WP#
for
RP#
A
A
A
A
A
A
V
A
A
A
A
A
A
A
A
A
A
PP
Figure 3. 40-Lead TSOP Pinout Diagram (Available in 4-Mbit Only)
16
15
14
13
12
11
18
9
8
7
6
5
4
3
2
1
product
the
extended
architecture
integration
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
family
temperature.
features
PP
of
, RP#, and
providing
several
10 mmx 20 mm
40-Lead TSOP
Boot Block
TOP VIEW
an
28F004B5
At
2.3.2
Each boot block component contains two parameter
blocks of 8 Kbytes (8,192 bytes) each to facilitate
storage of frequently updated small parameters that
would normally require an EEPROM. By using
software techniques, the byte-rewrite functionality
of EEPROMs can be emulated. These techniques
are detailed in Intel’s application note, AP-604
Using Intel’s Boot Block Flash Memory Parameter
Blocks to Replace EEPROM . The parameter blocks
are not write-protectable.
2.3.3
After the allocation of address space to the boot
and parameter blocks, the remainder is divided into
main blocks for data or code storage. Each device
contains one 96-Kbyte (98,304 byte) block and
additional 128-Kbyte (131,072 byte) blocks. The
2-Mbit has one 128-KB block; the 4-Mbit, three; and
the 8-Mbit, seven.
TWO 8-KB PARAMETER BLOCKS
MAIN BLOCKS - ONE 96-KB +
ADDITIONAL 128-KB BLOCKS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PRELIMINARY
A
GND
NC
NC
A
DQ
DQ
DQ
DQ
V
V
NC
DQ
DQ
DQ
DQ
OE#
GND
CE#
A
CC
CC
17
10
0
7
6
5
4
3
2
1
0