DT28F160S570 Intel, DT28F160S570 Datasheet - Page 9

• Manufacturer Part Number: DT28F160S570
• Manufacturer: Intel

Specifications of DT28F160S570

• Density: 16Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

2.0
The 5 Volt FlashFile memories include an on-chip
Write State Machine (WSM) to manage block
erase,
functions. It allows for: 100% TTL-level control
inputs, fixed power supplies during block erasure,
programming, lock-bit configuration, and minimal
processor overhead with RAM-like interface
timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations ), the
device defaults to read array mode. Manipulation
of external memory control pins allow array read,
standby, and output disable operations.
Read Array, status register, query, and identifier
codes can be accessed through the CUI
independent
programming voltage on V
28F016SV
28F016SA
RY/BY#
PRELIMINARY
CE #
CE #
DQ
DQ
GND
WE#
WP#
DQ
DQ
DQ
DQ
OE#
3/5#
DQ
A
V
DQ
V
A
A
A
A
A
A
A
A
NC
0
1
CC
CC
12
13
14
15
20
19
18
17
16
14
15
13
12
6
7
5
4
H ighlights pinout changes.
PRINCIPLES OF OPERATION
28F320S3
program,
28F320S5
CE #
CE #
DQ
DQ
GND
WE#
WP#
DQ
DQ
STS
DQ
DQ
OE#
DQ
DQ
A
V
V
A
A
A
A
NC
A
A
A
A
A
0
1
CC
CC
12
13
14
15
20
19
18
17
16
14
15
21
13
12
6
7
5
4
of
28F160S3
28F160S5
CE #
CE #
the
DQ
DQ
WE#
WP#
GND
DQ
DQ
STS
OE#
and
DQ
DQ
DQ
V
DQ
V
A
A
A
A
A
A
A
A
A
NC
NC
0
1
CC
CC
12
13
14
15
20
19
18
17
16
14
15
13
12
6
7
5
4
Figure 3. 28F320S5 and 28F160S5 SSOP 56-Lead Pinout
V
lock-bit
PP
PP
enables successful
1
2
3
4
5
6
7
8
9
10
11
12
13
15
16
17
18
19
20
21
22
23
24
25
26
27
28
14
voltage.
configuration
Proper
STANDARD PINOUT
16 mm x 23.7 mm
56-LEAD SSOP
TOP VIEW
block
configuration.
altering memory contents—block erase, program,
lock-bit
codes—are accessed via the CUI and verified
through the status register.
Commands are written using standard micro-
processor write timings. The CUI contents serve
as input to the WSM that controls the block
erase, programming, and lock-bit configuration.
The internal algorithms are regulated by the
WSM,
verification, and margining of data. Addresses
and data are internally latched during write
cycles. Writing the appropriate command outputs
array data, identifier codes, or status register
data.
Interface
progress of block erase, programming, and lock-
including
erasure,
configuration,
software
All
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
functions
pulse
program,
that
28F160S5/28F320S5
28F160S3
28F160S5
status,
R/P#
A
A
A
A
GND
DQ
V
A
A
A
A
A
A
A
V
DQ
DQ
DQ
A
BYTE#
NC
NC
DQ
DQ
DQ
DQ
GND
PP
3
6
7
CC
11
10
9
1
2
4
5
8
0
initiates
9
1
0
2
10
3
11
8
repetition,
associated
28F320S5
28F320S3
R/P#
A
V
A
A
A
A
A
A
A
A
A
GND
A
V
DQ
DQ
DQ
DQ
A
BYTE#
NC
NC
DQ
DQ
DQ
DQ
GND
and
and
PP
7
CC
11
10
9
1
2
3
4
5
6
8
0
9
1
0
2
10
11
8
3
and
identifier
28F016SV
28F016SA
internal
lock-bit
R/P#
V
A
A
A
A
A
A
A
A
A
GND
A
V
DQ
DQ
DQ
DQ
A
BYTE#
NC
NC
DQ
DQ
DQ
DQ
GND
A
PP
11
10
9
2
3
4
5
6
7
CC
1
8
0
polls
9
2
10
11
0609_03
1
8
0
3
with
9