UPD431000AGW-70LL Renesas Electronics America, UPD431000AGW-70LL Datasheet - Page 17

• Manufacturer Part Number: UPD431000AGW-70LL
• Manufacturer: Renesas Electronics America

Specifications of UPD431000AGW-70LL

• Density: 1Mb
• Access Time (max): 70ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 17b
• Package Type: SOP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 70mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Word Size: 8b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

Write Cycle Timing Chart 1 (/WE Controlled)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2.
I/O (Input / Output)
Address (Input)
2. Do not input data to the I/O pins while they are in the output state.
2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
/CE1 (Input)
CE2 (Input)
/WE (Input)
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
Indefinite data out
t
AS
Data Sheet M11657EJEV0DS
t
WHZ
t
AW
t
t
CW1
CW2
t
WC
impe-
dance
High
t
WP
t
DW
Data in
t
t
WR
DH
t
OW
High
impe-
dance
Indefinite data out
μ
PD431000A
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