CY7C128A-45PC Cypress Semiconductor Corp, CY7C128A-45PC Datasheet - Page 4
![no-image](/images/manufacturer_photos/0/1/179/cypress_semiconductor_corp_sml.jpg)
CY7C128A-45PC
Manufacturer Part Number
CY7C128A-45PC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C128A-45PC.pdf
(9 pages)
Specifications of CY7C128A-45PC
Density
16Kb
Access Time (max)
45ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
5V
Address Bus
11b
Package Type
PDIP
Operating Temp Range
0C to 70C
Number Of Ports
1
Supply Current
120mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
24
Word Size
8b
Number Of Words
2K
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C128A-45PC
Manufacturer:
ATMEL
Quantity:
2 889
Part Number:
CY7C128A-45PC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Capacitance
AC Test Loads and Waveforms
Switching Characteristics
Document #: 38-05028 Rev. *B
OUTPUT
READ CYCLE
t
t
t
t
t
t
t
t
t
t
t
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
Notes:
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
HZWE
LZWE
4. Tested initially and after any design or process changes that may affect these parameters
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
6. t
7. At any given temperature and voltage condition, t
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write
Parameter
I
by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
OL
HZOE
INCLUDING
5V
/I
OH
Parameter
, t
JIG AND
SCOPE
and 30-pF load capacitance.
HZCE
C
30 pF
C
OUT
, and t
IN
[8]
HZWE
[4]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
R1 481
(a)
are specified with C
R2
255
Input Capacitance
Output Capacitance
OUTPUT
L
Description
Description
= 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady state voltage.
[7]
Over the Operating Range
[6, 7]
[6]
[6]
INCLUDING
5V
JIG AND
HZCE
SCOPE
5 pF
is less than t
R1 481
(b)
LZCE
T
V
for any given device.
A
CC
R2
255
= 25C, f = 1 MHz,
C128A–4
= 5.0V
[2, 5]
Test Conditions
Min.
20
20
15
15
15
10
5
3
5
0
0
0
0
5
GND
3.0V
Equivalent to:
-20
5 ns
Max.
20
20
10
20
10%
8
8
7
OUTPUT
ALL INPUT PULSES
90%
THÉ VENIN EQUIVALENT
Min.
45
40
30
30
20
15
5
3
5
0
0
0
0
5
Max.
10
10
-45
167
Max.
45
45
20
15
15
25
15
90%
CY7C128A
10%
Unit
5 ns
1.73V
pF
pF
C128A–5
Unit
Page 4 of 9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback