AM29F200BB-90SE Spansion Inc., AM29F200BB-90SE Datasheet - Page 14
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AM29F200BB-90SE
Manufacturer Part Number
AM29F200BB-90SE
Description
Manufacturer
Spansion Inc.
Datasheet
1.AM29F200BB-90SE.pdf
(41 pages)
Specifications of AM29F200BB-90SE
Cell Type
NOR
Density
2Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
18/17Bit
Operating Supply Voltage (typ)
5V
Operating Temp Range
-55C to 125C
Package Type
SOIC
Program/erase Volt (typ)
4.5 to 5.5V
Sync/async
Asynchronous
Operating Temperature Classification
Military
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Word Size
8/16Bit
Number Of Words
256K/128K
Supply Current
50mA
Mounting
Surface Mount
Pin Count
44
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AM29F200BB-90SE
Manufacturer:
AMD
Quantity:
5 380
Company:
Part Number:
AM29F200BB-90SE
Manufacturer:
SPANSION
Quantity:
1 545
Company:
Part Number:
AM29F200BB-90SE
Manufacturer:
AMD
Quantity:
6 227
Part Number:
AM29F200BB-90SE
Manufacturer:
AMD
Quantity:
20 000
gramming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.
Low V
When V
accept any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. The Command Definitions table defines the
valid register command sequences. Writing incorrect
address and data values or writing them in the
improper sequence resets the device to reading array
data.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
12
CC
CC
Write Inhibit
is less than V
LKO
CC
. The system must provide the
is greater than V
LKO
, the device does not
CC
LKO
power-up and
.
D A T A
Am29F200B
CC
CC
S H E E T
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
ters, and Read Operation Timings diagram shows the
timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies dur ing Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
The Command Definitions table shows the address
and data requirements. This method is an alternative to
that shown in the Autoselect Codes (High Voltage
IL
, CE# = V
IH
or WE# = V
IL
and OE# = V
IH
. To initiate a write cycle,
IH
21526D6 August 3, 2009
during power up, the