MC14549BCP ON Semiconductor, MC14549BCP Datasheet - Page 5

• Manufacturer Part Number: MC14549BCP
• Manufacturer: ON Semiconductor

Specifications of MC14549BCP

• Logic Family: 4000
• Logical Function: Succ Approx Reg
• Number Of Elements: 1
• Number Of Bits: 8
• Number Of Inputs: 1
• Number Of Outputs: 8
• High Level Output Current: -4.2mA
• Low Level Output Current: 4.2mA
• Package Type: PDIP
• Propagation Delay Time: 1000ns
• Operating Supply Voltage (typ): 3.3/5/9/12/15V
• Operating Supply Voltage (max): 18V
• Operating Supply Voltage (min): 3V
• Output Type: Standard
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 4(Typ)MHz
• Mounting: Through Hole
• Pin Count: 16
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Quiescent Current: 20uA
• Lead Free Status / Rohs Status: Not Compliant

either the “free run” or “strobed operation” mode for
conversion schemes with any number of bits. Reliable
cascading and/or recirculating operation can be achieved if
the End of Convert (EOC) output is used as the controlling
function, since with EOC = 0 (and with SC = 1 for
MC14549B but either 1 or 0 for MC14559B) no stable state
exists under continual clocked operation. The MC14559B
will automatically recirculate after EOC = 1 during externally
strobed operation, provided SC = 1.
into the circuit on the positive edge of the clock pulse.
required for data on any input to be strobed into the circuit.
on the positive−going transition of the SC input on
succeeding clock cycles.
comparator in A/D applications) is also entered into the
circuit on a positive−going transition of the clock. This input
is Schmitt triggered and synchronized to allow fast response
and guaranteed quality of serial and parallel data.
output to 0 on positive−going transitions of the clock. If
removed while SC = 0, the circuit will remain reset until
SC = 1. This allows easy cascading of circuits.
register shortening by removing unwanted bits from a system.
the least significant bit of the circuit to EOC. E.g., for a 6−bit
Both the MC14549B and MC14559B can be operated in
All data and control inputs for these devices are triggered
Operation of the various terminals is as follows:
C = Clock — A positive−going transition of the Clock is
SC = Start Convert — A conversion sequence is initiated
D = Data in — Data on this input (usually from a
MR = Master Reset (MC14549B Only) — Resets all
FF = Feed Forward (MC14559B Only) — Provides
For operation with less than 8 bits, tie the output following
** Cascading using EOC guaranteed; no stable unfunctional state.
†Completion of conversion automatically re−initiates cycle in free run mode.
* FF allows EOC to activate as if in 4−stage register.
*
MSB
C
SC
FF
Q7 Q6 Q5 Q4
TO D/A AND PARALLEL DATA
COMPARATOR
MC14559B
FROM A/D
D
••
Q0 EOC
NC
S
Figure 1. 12−Bit Conversion Scheme
OPERATING CHARACTERISTICS
out
**
MC14549B, MC14559B
EXTERNAL
CLOCK
EXTERNAL STROBE
http://onsemi.com
C
SC
MR
FREE RUN MODE
Q7 Q6 Q5
5
PARALLEL DATA
TO D/A AND
conversion, tie Q1 to FF; the part will respond as shown in the
timing diagram less two bit times. Not that Q1 and Q0 will
still operate and must be disregarded.
the basic connections shown in Figure 1. The FF input of the
MC14559B is used to shorten the setup. Tying FF directly to
the least significant bit used in the MC14559B allows EOC
to provide the cascading signal, and results in smooth
transition of serial information from the MC14559B to the
MC14549B. The Serial Out (S
MC14559B remains inactive one cycle after EOC goes high,
while S
second clock cycle of its operation.
Q’s on succeeding cycles go high and are then conditionally
reset dependent upon the state of the D input. Once
conditionally reset they remain in the proper state until the
circuit is either reset or reinitiated.
negative−going transition of the clock following FF = 1 (for
the MC14559B) or the conditional reset of Q0. This allows
settling of the digital circuitry prior to the End of Conversion
indication. Therefore either level or edge triggering can
indicate complete conversion.
fashion. Serial data occurs during the clock period when the
corresponding parallel data bit is conditionally reset. Serial
Out is inhibited on the initial period of a cycle, when the
circuit is reset, and on the second cycle after EOC goes high.
This provides efficient operation when cascaded.
MC14549B
Q4 Q3 Q2 Q1 Q0 EOC
For 8−bit operation, FF is tied to V
For applications with more than 8 but less than 16 bits, use
Q
EOC = End of Convert — This output goes high on the
S
out
D
n
= Data Outputs — After a conversion is initiated the
= Serial Out — Transmits conversion in serial
out
of the MC14549B remains inhibited until the
LSB
S
out
{
1/4 MC14001
out
) inhibit structure of the
SERIAL OUT
(CONTINUAL
UPDATE EVERY
13 CLOCK CYCLES)
SS
.