AT49LW040-33JC Atmel, AT49LW040-33JC Datasheet - Page 13

• Manufacturer Part Number: AT49LW040-33JC
• Manufacturer: Atmel

Specifications of AT49LW040-33JC

• Cell Type: NOR
• Density: 4Mb
• Access Time (max): 30ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 4/11Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 85C
• Package Type: PLCC
• Program/erase Volt (typ): 3 to 3.6V
• Sync/async: Async/Sync
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 512K
• Supply Current: 67mA
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

3342A–FLASH–6/03
READ LOCK: The default read status of all sectors upon power-up is read-unlocked.
When a sector’s read-lock bit is set (1 state), data cannot be read from that sector. An
attempted read from a read-locked sector will result in data 00H being read. (Note that
failure is not reflected in the status register). The read-lock status can be unlocked by
clearing (0 state) the read-lock bit, provided the lock-down bit has not been set. The cur-
rent read-lock status of a particular sector can be determined by reading the
corresponding read-lock bit.
WRITE LOCK: The default write status of all sectors upon power-up is write-locked (1
state). Any program or erase operations attempted on a locked sector will return an
error in the status register (indicating sector lock). The status of the locked sector can be
changed to unlocked (0 state) by clearing the write-lock bit, provided the lock-down bit is
not also set. The current write-lock status of a particular sector can be determined by
reading the corresponding write-lock bit. Any program or erase operations attempted on
a locked sector will return an error in the status register (indicating sector lock). The
write-lock functions in conjunction with the hardware write-lock pins, TBL and WP.
When active, these pins take precedence over the register-locking function and
write-lock the top sector or remaining sectors, respectively. Reading this register will not
read the state of the TBL or WP pins.
LOCK-DOWN: When in the FWH interface mode, the default lock-down status of all
sectors upon power-up is not-locked-down (0 state). The lock-down bit for any sector
may be set (1 state), but only once, as future attempted changes to that sector locking
register will be ignored. The lock-down bit is only cleared upon a device reset with RST
or INIT. The current lock-down status of a particular sector can be determined by read-
ing the corresponding lock-down bit. Once a sector’s lock-down bit is set, the read- and
write-lock bits for that sector can no longer be modified and the sector is locked down in
its current state of read and write accessibility.
GENERAL-PURPOSE INPUTS REGISTER: This register reads the status of the
FGPI[4:0] pins on the FWH at power-up. Since this is a pass-through register, there is
no default value as shown in Table 7. It is recommended that the GPI pins be in the
desired state before FWH4 is brought low for the beginning of the next bus cycle, and
remain in that state until the end of the cycle.
Table 10. General-purpose Input Registers
Bit
7:5
4
3
2
1
0
Function
Reserved
FGPI[4]
Reads status of general-purpose input pin (PLCC-30/TSOP-7)
FGPI[3]
Reads status of general-purpose input pin (PLCC-3/TSOP-15)
FGPI[2]
Reads status of general-purpose input pin (PLCC-4/TSOP-16)
FGPI[1]
Reads status of general-purpose input pin (PLCC-5/TSOP-17)
FGPI[0]
Reads status of general-purpose input pin (PLCC-6/TSOP-18)
AT49LW040
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