P80C31BH Intel, P80C31BH Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
P80C31BH
Manufacturer Part Number
P80C31BH
Description
Manufacturer
Intel
Datasheet
1.P80C31BH.pdf
(16 pages)
Specifications of P80C31BH
Cpu Family
MCS51
Device Core
8051
Device Core Size
8b
Frequency (max)
16MHz
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
128Byte
# I/os (max)
32
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 125C
Operating Temperature Classification
Automotive
Mounting
Through Hole
Pin Count
40
Package Type
PDIP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P80C31BH
Manufacturer:
INT
Quantity:
3 000
Company:
Part Number:
P80C31BH
Manufacturer:
INT
Quantity:
3 000
Company:
Part Number:
P80C31BH
Manufacturer:
INT
Quantity:
5 510
Part Number:
P80C31BH
Manufacturer:
INTEL
Quantity:
20 000
Company:
Part Number:
P80C31BH-1
Manufacturer:
INT
Quantity:
6 100
Part Number:
P80C31BH-1
Manufacturer:
INTEL
Quantity:
20 000
Program Verification
(EPROM Only)
If Lock Bit 2 has not been programmed the on-chip
Program Memory can be read out for program verifi-
cation The address of the Program Memory location
to be read is applied to Ports 1 and 2 as shown in
Figure 13 The other pins are held at the ‘‘Verify
Code Data’’ levels indicated in Table 3 The con-
tents of the addressed location will be emitted on
Port 0 External pullups are required on Port 0 for
this operation Detailed timing specifications are
shown in later sections of this datasheet
If the Encryption Table has been programmed the
data presented at Port 0 will be the Exclusive NOR
of the program byte with one of the encryption bytes
The user will have to know the Encryption Table
contents in order to correctly decode the verification
data The Encryption Table itself can not be read
out
Reading the Signature Bytes
(EPROM Only)
The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031H
except that P3 6 and P3 7 need to be pulled to a
logic low The values returned are
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(T
A
(030H)
(031H)
e
V
I
1 T
T
T
T
T
T
T
T
T
T
T
T
T
Symbol
PP
PP
AVGL
GHAX
DVGL
GHDX
EHSH
SHGL
GHSL
GLGH
AVQV
ELQV
EHQZ
GHGL
21 C to 27 C V
CLCL
e
e
89H indicates manufactured by Intel
57H indicates 87C51
CC
Programming Supply Voltage
Programming Supply Current
Oscillator Frequency
Address Setup to PROG Low
Address Hold After PROG
Data Setup to PROG Low
Data Hold After PROG
P2 7 (ENABLE) High to V
V
V
PROG Width
Address to Data Valid
ENABLE Low to Data Valid
Data Float After ENABLE
PROG High to PROG Low
PP
PP
e
Setup to PROG Low
Hold After PROG
5V
Parameter
g
20% V
SS
e
PP
0V)
Program Verify Algorithms
(EPROM Only)
Any algorithm in agreement with the conditions list-
ed in Table 3 and which satisfies the timing specifi-
cations is suitable
Erasure Characteristics
(EPROM Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelengths shorter
than approximately 4 000 Angstroms Since sunlight
and fluorescent lighting have wavelengths in this
range exposure to these light sources over an ex-
tended time (about 1 week in sunlight or 3 years in
room level fluorescent lighting) could cause inadver-
tent erasure If an application subjects the device to
this type of exposure it is suggested that an opaque
label be placed over the window
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrat-
ed dose of at least 15 W-sec cm
EPROM to an ultraviolet lamp of 12 000
rating for 30 minutes at a distance of about 1 inch
should be sufficient
Erasure leaves the array in an all 1s state
AUTOMOTIVE 80C31BH 80C51BH 87C51
48T
48T
48T
48T
48T
12 5
Min
10
10
90
10
4
0
CLCL
CLCL
CLCL
CLCL
CLCL
48T
48T
48T
Max
13 0
110
50
6
CLCL
CLCL
CLCL
2
Exposing the
Units
MHz
mA
V
W cm
s
s
s
s
15
2