NLAST44599DTG ON Semiconductor, NLAST44599DTG Datasheet
NLAST44599DTG
Specifications of NLAST44599DTG
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NLAST44599DTG Summary of contents
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NLAST44599 Low Voltage Single Supply Dual DPDT Analog Switch The NLAST44599 is an advanced CMOS dual−independent DPDT (double pole−double throw) analog switch, fabricated with silicon gate CMOS technology. It achieves high−speed propagation delays and low ON resistances while maintaining CMOS ...
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QFN−16 PACKAGE SAB See TSSOP−16 Switch Configuration COM TSSOP−16 PACKAGE COM ELECT ...
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MAXIMUM RATINGS Symbol V Positive DC Supply Voltage CC V Analog Input Voltage ( Digital Select Input Voltage Current, Into or Out of Any Pin IK P Power Dissipation in Still Air ...
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DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) Symbol Parameter V Minimum High−Level Input IH Voltage, Select Inputs V Maximum Low−Level Input IL Voltage, Select Inputs I Maximum Input Leakage IN Current I Power Off Leakage Current, OFF Select ...
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AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Turn−On Time ON (Figures 12 and 13) t Turn−Off Time OFF (Figures 12 and 13) t Minimum Break−Before−Make BBM Time *Typical Characteristics are at 25°C. C Maximum Input Capacitance, Select Input ...
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DUT V Output CC 0.1 mF 300 W Switch Select Pin DUT V Output CC 0.1 mF Open Input DUT Output Open Input V CC Input GND V OUT 35 pF Output GND Figure 4. t (Time Break−Before−Make) BBM V ...
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W Generator Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth switch. V ISO V = Off Channel Isolation = 20 Log ISO V = ...
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Off Isolation −60 −80 −100 0.01 0.1 1 FREQUENCY (MHz) Figure 10. Off−Channel Isolation (ns (ns) 5 OFF 0 2 (VOLTS) CC Figure 12. t ...
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0.001 0.0001 0.00001 −40 − Temperature (°C) Figure 16. I vs. Temp 100 125°C ...
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V (VDC) IS Figure 22. R vs. Temp DEVICE ORDERING INFORMATION Circuit Device Order Indicator Number Technology NLAST44599DT NL NLAST44599DTR2 NL ...
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D Î Î Î PIN 1 Î Î Î LOCATION 0.15 C TOP VIEW 0.15 C DETAIL B (A3) 0. 0.08 C SIDE VIEW D2 DETAIL 16X 5 8 EXPOSED PAD NOTE 5 4 ...
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... −V− C 0.10 (0.004) −T− SEATING D PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE Ï Ï Ï ...
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... SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...