MT48LC32M16A2P-75:CTR Micron Technology Inc, MT48LC32M16A2P-75:CTR Datasheet - Page 29

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MT48LC32M16A2P-75:CTR

Manufacturer Part Number
MT48LC32M16A2P-75:CTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48LC32M16A2P-75:CTR

Organization
32Mx16
Density
512Mb
Address Bus
15b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
115mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Figure 18:
Figure 19:
PDF: 09005aef809bf8f3/Source: 09005aef80818a4a
512MbSDRAM.fm - Rev. L 10/07 EN
WRITE Burst
WRITE-to-WRITE
Note:
Note:
COMMAND
Data for any WRITE burst may be truncated with a subsequent READ command, and
data for a fixed-length WRITE burst may be immediately followed by a READ command.
After the READ command is registered, the data inputs will be ignored, and WRITEs will
not be executed. An example is shown in Figure 21 on page 30. Data n + 1 is either the
last of a burst of two or the last desired of a longer burst.
COMMAND
ADDRESS
ADDRESS
BL = 2. DQM is LOW.
DQM is LOW. Each WRITE command may be to any bank.
CLK
CLK
DQ
DQ
Transitioning Data
WRITE
WRITE
BANK,
COL n
BANK,
COL n
D
T0
D
T0
n
IN
n
IN
Transitioning Data
n + 1
NOP
n + 1
NOP
D
T1
T1
D
IN
IN
29
Don’t Care
WRITE
BANK,
COL b
NOP
T2
T2
D
b
IN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Don’t Care
T3
NOP
512Mb: x4, x8, x16 SDRAM
©2000 Micron Technology, Inc. All rights reserved.
Operations

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