PC28F512P30EFA Micron Technology Inc, PC28F512P30EFA Datasheet - Page 36

• Manufacturer Part Number: PC28F512P30EFA
• Manufacturer: Micron Technology Inc

Specifications of PC28F512P30EFA

• Cell Type: NOR
• Density: 512Mb
• Interface Type: Parallel/Serial
• Address Bus: 25b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: BGA
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 32M
• Supply Current: 31mA
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

Table 13: Read Configuration Register Description (Sheet 2 of 2)
11.2.1
11.2.2
Datasheet
36
3
2:0
Burst Wrap (BW)
Burst Length (BL[2:0])
Read Mode (RCR.15)
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count (RCR[14:11])
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and
settings of LC. The maximum Latency Count for P30-65nm would be Code 5 based on
the Max clock frequency specification of 52MHz, and there will be zero WAIT States
when bursting within the word line. Please also refer to
Line (EOWL) Considerations” on page 38
Refer to
Table 14, “LC and Frequency Support” on page 37
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Figure 10
shows the data output latency for the different
for more information on EOWL.
Section 11.2.3, “End of Word
for Latency Code Settings.
Order Number: 208042-05
P30-65nm
Apr 2010