M45PE20-VMN6P Micron Technology Inc, M45PE20-VMN6P Datasheet - Page 23

• Manufacturer Part Number: M45PE20-VMN6P
• Manufacturer: Micron Technology Inc

Specifications of M45PE20-VMN6P

• Cell Type: NOR
• Density: 2Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC N
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 256K
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

M45PE20
6.6
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on serial data output (Q), each bit
being shifted out, at a maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing
the read sequence to be continued indefinitely.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip
Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read
data bytes at higher speed (FAST_READ) instruction, while an erase, program or write cycle
is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 11. Read data bytes at higher speed (FAST_READ) instruction sequence
1. Address bits A23 to A18 are don’t care.
S
C
D
Q
S
C
D
Q
0
and data-out sequence
7
32 33 34
1
High Impedance
6
2
Instruction
Dummy byte
5
3
4
4
35
3
36 37 38 39 40 41 42 43 44 45 46
5
2
6
1
7
23
0
8
MSB
22 21
7
Figure
9 10
24-bit address
6
DATA OUT 1
5
C
11.
, during the falling edge of Serial Clock (C).
3
28 29 30 31
4
2
3
1
2
0
1
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
Instructions
0
MSB
7
AI04006
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