M25P10-AVMN6TP Micron Technology Inc, M25P10-AVMN6TP Datasheet - Page 13
M25P10-AVMN6TP
Manufacturer Part Number
M25P10-AVMN6TP
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25P10-AVMN6TP.pdf
(38 pages)
Specifications of M25P10-AVMN6TP
Lead Free Status / Rohs Status
Compliant
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Figure 8. Write Enable (WREN) Instruction Sequence
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
Figure 9. Write Disable (WRDI) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
S
C
D
Q
S
C
D
Q
High Impedance
0
High Impedance
0
1
1
2
2
Instruction
Instruction
3
3
4
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction com-
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
4
5
pletion
5
6
6
7
7
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