MT48H8M16LFB4-75 IT:KTR Micron Technology Inc, MT48H8M16LFB4-75 IT:KTR Datasheet - Page 48
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MT48H8M16LFB4-75 IT:KTR
Manufacturer Part Number
MT48H8M16LFB4-75 IT:KTR
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT48H8M16LFB4-75_ITKTR.pdf
(86 pages)
Specifications of MT48H8M16LFB4-75 IT:KTR
Lead Free Status / Rohs Status
Compliant
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Figure 17: Consecutive READ Bursts
PDF: 09005aef832ff1ea
128mb_mobile_sdram_y35M.pdf - Rev. G 10/09 EN
Note:
Command
Command
Address
Address
1. Each READ command can be issued to any bank. DQM is LOW.
CLK
CLK
DQ
DQ
T0
T0
Bank,
READ
READ
Col n
Bank,
Col n
CL = 2
CL = 3
T1
T1
NOP
NOP
128Mb: 8 Meg x 16, 4 Meg x 32 Mobile SDRAM
48
T2
T2
NOP
NOP
D
OUT
n
T3
T3
NOP
NOP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
D
D
n + 1
OUT
OUT
READ
T4
READ
T4
Bank,
Bank,
Col b
Col b
X = 1 cycle
D
n + 2
D
Transitioning data
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
D
D
n + 3
OUT
OUT
©2008 Micron Technology, Inc. All rights reserved.
T6
T6
NOP
NOP
READ Operation
D
D
OUT
OUT
b
Don’t Care
T7
NOP
D
OUT
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