HI-3584PQI-10 Holt Integrated Circuits, HI-3584PQI-10 Datasheet
HI-3584PQI-10
Specifications of HI-3584PQI-10
Related parts for HI-3584PQI-10
HI-3584PQI-10 Summary of contents
Page 1
... The independent transmitter also has FIFO The status of all three FIFOs can be monitored using . the external status pins or by polling the HI-3584’s status register. Other new features include a programmable option of data or parity in the 32nd bit, and the ability to unscramble the 32 bit word ...
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... PL2 INPUT Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow TX/R OUTPUT Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. HFT OUTPUT Transmitter FIFO Half Full FFT ...
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... FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3584 contains a 16-bit control register which is used to con- figure the device. The control register bits CR0 - CR15 are loaded from BD00 - BD15 when CWSTR is pulsed low. The control regis- ter contents are output on the databus when SEL = 1 and pulsed low ...
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... Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register ...
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... CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation ...
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... PL2 the 31 bit word (or 32 bit word if CR4=0) in the next available position of the FIFO. If TX/R, the transmitter ready flag is high (FIFO empty), then words, each bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 32 positions are full, the FIFO ignores further attempts to load data ...
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... The parity generator counts the Ones in the 31-bit word. control register bit CR12 is set low, the 32nd bit transmitted will make parity odd. If the control bit is, high the parity is even. Setting CR4 to a Zero bypasses the parity generator, and allows 32 bits of data to be transmitted. ...
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... ARINC DATA BIT 31 BIT 32 D D/R DON'T CARE SEL EN DATA BUS t DATA BUS PL1 PL2 TX/R, HFT FFT , DATA BUS CWSTR HI-3584 DATA RATE - EXAMPLE PATTERN DATA DATA NULL NULL BIT 32 BIT 31 RECEIVER OPERATION t t SELEN t SELEN ENSEL t t ENEN D/REN t DATAEN ...
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... PL1 PL2 / CWSTR CWSTR EN1 EN2 / t CWHLD t CWSET DATA BUS Set CR1=1 Label #1 t ENDATA HI-3584 STATUS REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA CONTROL REGISTER READ CYCLE DON'T CARE t SELEN DATA VALID t ENDATA LABEL MEMORY LOAD SEQUENCE Label #2 t ...
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... ENDAT 429DO 429DO BIT 32 RIN D D/R D/REN EN t SELEN SEL DON'T CARE t ENPL PL1 PL2 TXR ENTX 429DO 429DO HI-3584 TRANSMITTING DATA ARINC BIT ARINC BIT DATA DATA BIT 1 BIT 2 One Null Zero Null REPEATER OPERATION TIMING t END ENEN EN t ENSEL ...
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... To GND Input Sink I IH Input Source I IL Differential C (RIN1A to RIN1B, RIN2A to RIN2B GND Input Voltage Input Voltage Input Sink I IH Input Source I IL Input Voltage Input Voltage Input Sink I IH Input Source Output Sink OUT Output Source OUT Output Sink OUT ...
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... Spacing - Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX LOW Delay - ENTX HIGH to TXAOUT or TXBOUT: High Speed Delay - ENTX HIGH to TXAOUT or TXBOUT: Low Speed REPEATER OPERATION TIMING Delay - TX/R LOW to ENTX HIGH MASTER RESET PULSE WIDTH ARINC DATA RATE AND BIT TIMING ...
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... FLOW I -40°C TO +85°C T -55°C TO +125°C PACKAGE DESCRIPTION CJ 52 PIN J-LEAD CERQUAD (52U) not available Pb-free PC 64 PIN PLASTIC CHIP-SCALE LPCC (64PCS PIN PLASTIC QUAD FLAT PACK PQFP (52PQS) HOLT INTEGRATED CIRCUITS 13 CWSTR 429DO FFT HFT PL2 PL1 ...
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... PLASTIC QUAD FLAT PACK (PQFP) .520 BSC SQ (13.2) .063 (1.6) See Detail A .084 .013 ± (2.13 ± .32) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-3584 PACKAGE DIMENSIONS max .788 (20.0) SQ. .750 .007 (19.05 .18) .190 max (4 ...
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... PLASTIC CHIP-SCALE PACKAGE .354 BSC (9.00) .354 Top View BSC (9.00) .039 max (1.00) HI-3584 PACKAGE DIMENSIONS Heat sink pad on bottom of package. Heat sink can float or can be connected to VDD. DO NOT connect heat sink to GND .281 ± .006 (7.15 ± .15 ) .016 ± .004 (0.40 ± ...