MT47H64M8B6-3 L:D Micron Technology Inc, MT47H64M8B6-3 L:D Datasheet - Page 83

• Manufacturer Part Number: MT47H64M8B6-3 L:D
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H64M8B6-3 L:D

• Organization: 64Mx8
• Density: 512Mb
• Address Bus: 16b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 180mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 40: Burst Definition
Operating Mode
DLL RESET
PDF: 09005aef82f1e6e2
Rev. M 9/08 EN
Burst Length
4
8
Starting Column Address
The normal operating mode is selected by issuing a command with bit M7 set to “0,”
and all other bits set to the desired values, as shown in Figure 38 (page 81). When bit M7
is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1”
places the DDR2 SDRAM into a test mode that is only used by the manufacturer and
should not be used. No operation or functionality is guaranteed if M7 bit is “1.”
DLL RESET is defined by bit M8, as shown in Figure 38 (page 81). Programming bit M8
to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns
back to a value of “0” after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the
(A2, A1, A0)
t
AC or
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0
0 1
1 0
1 1
t
DQSCK parameters.
Burst Type = Sequential
83
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Order of Accesses Within a Burst
512Mb: x4, x8, x16 DDR2 SDRAM
Burst Type = Interleaved
Mode Register (MR)
© 2004 Micron Technology, Inc. All rights reserved.
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0