LFE3-150EA-6FN672C Lattice, LFE3-150EA-6FN672C Datasheet - Page 95
LFE3-150EA-6FN672C
Manufacturer Part Number
LFE3-150EA-6FN672C
Description
IC FPGA 149KLUTS 380I/O 672-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-150EA-6FN672C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1221
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Table 3-12. External Reference Clock Specification (refclkp/refclkn)
Lattice Semiconductor
SERDES External Reference Clock
The external reference clock selection and its interface are a critical part of system applications for this product.
Table 3-12 specifies reference clock requirements, over the full range of operating conditions.
Figure 3-13. SERDES External Reference Clock Waveforms
F
F
V
V
V
D
T
T
Z
C
1. Depending on the application, the PLL_LOL_SET and CDR_LOL_SET control registers may be adjusted for other tolerance values as
2. The signal swing for a single-ended input clock must be as large as the p-p differential swing of a differential input clock to get the same gain
3. Measured at 50% amplitude.
REF
REF-PPM
REF-R
REF-F
REF-IN-TERM-DIFF
REF-IN-SE
REF-IN-DIFF
REF-IN
REF
REF-IN-CAP
described in TN1176,
at the input receiver. Lower swings for the clock may be possible, but will tend to increase jitter.
Symbol
Frequency range
Frequency tolerance
Input swing, single-ended clock
Input swing, differential clock
Input levels
Duty cycle
Rise time (20% to 80%)
Fall time (80% to 20%)
Differential input termination
Input capacitance
LatticeECP3 SERDES/PCS Usage
3
Description
1
2
Guide.
3-42
-1000
-20%
Min.
200
200
200
200
15
40
—
0
DC and Switching Characteristics
100/2K
Typ.
LatticeECP3 Family Data Sheet
500
500
—
—
—
—
—
—
—
V
CCA
2*V
+20%
V
Max.
1000
1000
1000
320
CCA
60
7
CCA
+ 0.3
differential
mV, p-p
mV, p-p
Ohms
Units
MHz
ppm
pF
ps
ps
%
V
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