LFE3-95EA-8FN1156C Lattice, LFE3-95EA-8FN1156C Datasheet - Page 28
LFE3-95EA-8FN1156C
Manufacturer Part Number
LFE3-95EA-8FN1156C
Description
IC FPGA 92KLUTS 490I/O 1156-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-95EA-8FN1156C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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MAC DSP Element
In this case, the two operands, AA and AB, are multiplied and the result is added with the previous accumulated
value. This accumulated value is available at the output. The user can enable the input and pipeline registers, but
the output register is always enabled. The output register is used to store the accumulated value. The ALU is con-
figured as the accumulator in the sysDSP slice in the LatticeECP3 family can be initialized dynamically. A regis-
tered overflow signal is also available. The overflow conditions are provided later in this document. Figure 2-27
shows the MAC sysDSP element.
Figure 2-27. MAC DSP Element
DSP Slice
Previous
IR = Input Register
PR = Pipeline Register
OR = Output Register
FR = Flag Register
Rounding
SRIB
SRIA
C_ALU
A_ALU
CIN
0
I
C
IR
AA
MULTA
OR
PR
AMUX
A_ALU
IR
From FPGA Core
AB
To FPGA Core
0
R = Logic (B, C)
R= A ± B ± C
2-25
OR
PR
IR
OPCODE
FR
0
=
=
B_ALU
BMUX
IR
ALU
BA
MULTB
LatticeECP3 Family Data Sheet
PR
OR
IR
BB
IR
COUT
SROB
SROA
DSP Slice
Next
Architecture
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