LFE2-50E-7FN672C Lattice, LFE2-50E-7FN672C Datasheet - Page 72

• Manufacturer Part Number: LFE2-50E-7FN672C
• Description: IC FPGA 50KLUTS 500I/O 672-BGA
• Manufacturer: Lattice

Specifications of LFE2-50E-7FN672C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LatticeECP2/M External Switching Characteristics
t
t
t
Lattice Semiconductor
SUE
HE
SU_DELE
Parameter
Clock to Data Setup - PIO Input
Register
Clock to Data Hold - PIO Input
Register
Clock to Data Setup - PIO Input
Register with Data Input Delay
Description
Over Recommended Operating Conditions
LFE2-6
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
LFE2-6
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
LFE2-6
LFE2-12
LFE2-20
LFE2-35
LFE2-50
LFE2-70
LFE2M20
LFE2M35
LFE2M50
LFE2M70
LFE2M100
Device
3-21
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
1.20
1.20
1.20
1.00
1.00
1.00
1.00
1.00
1.00
1.20
1.20
1.20
1.20
1.20
-7
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
9
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
1.10
1.10
1.10
1.10
1.10
1.10
1.10
1.10
1.40
1.40
1.40
1.30
1.30
1.30
1.30
1.30
1.30
1.60
1.60
1.60
1.60
1.60
(Continued)
-6
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
0.00
1.30
1.30
1.30
1.30
1.30
1.30
1.30
1.30
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.60
1.90
1.90
1.90
1.90
1.90
-5
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns