LFXP2-40E-6FN484I Lattice, LFXP2-40E-6FN484I Datasheet - Page 22

• Manufacturer Part Number: LFXP2-40E-6FN484I
• Description: IC FPGA 40KLUTS 363I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFXP2-40E-6FN484I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-19. Comparison of General DSP and LatticeXP2 Approaches
sysDSP Block Capabilities
The sysDSP block in the LatticeXP2 family supports four functional elements in three 9, 18 and 36 data path
widths. The user selects a function element for a DSP block and then selects the width and type (signed/unsigned)
of its operands. The operands in the LatticeXP2 family sysDSP Blocks can be either signed or unsigned but not
mixed within a function element. Similarly, the operand widths cannot be mixed within a block. DSP elements can
be concatenated.
The resources in each sysDSP block can be configured to support the following four elements:
• MULT (Multiply)
• MAC (Multiply, Accumulate)
• MULTADDSUB (Multiply, Addition/Subtraction)
• MULTADDSUBSUM (Multiply, Addition/Subtraction, Accumulate)
The number of elements available in each block depends on the width selected from the three available options: x9,
x18, and x36. A number of these elements are concatenated for highly parallel implementations of DSP functions.
Table 2-6 shows the capabilities of the block.
Table 2-6. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift register from previous operand registers. By selecting ‘dynamic operation’ the following operations
are possible:
MULT
MAC
MULTADDSUB
MULTADDSUBSUM
Width of Multiply
Accumulator
Multiplier
Single
Operand
Function implemented in
General purpose DSP
A
x
Operand
B
M loops
x9
8
2
4
2
Operand
A
x
Operand
Multiplier 0
B
2-19
Multiplier 1
Operand
A
accumulate
Function implemented
x
(k adds)
m/k
Operand
in LatticeXP2
B
+ +
x18
4
2
2
1
Output
LatticeXP2 Family Data Sheet
Operand
A
x
Operand
Multiplier k
B
loops
m/k
Architecture
x36
—
—
—
1