LFE3-35EA-8FN484C Lattice, LFE3-35EA-8FN484C Datasheet - Page 118
LFE3-35EA-8FN484C
Manufacturer Part Number
LFE3-35EA-8FN484C
Description
IC FPGA 33KLUTS 295I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFE3-150EA-7FN672C.pdf
(136 pages)
Specifications of LFE3-35EA-8FN484C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Signal Descriptions (Cont.)
Lattice Semiconductor
D7/SPID0
DI/CSSPI0N/CEN
Dedicated SERDES Signals
PCS[Index]_HDINNm
PCS[Index]_HDOUTNm
PCS[Index]_REFCLKN
PCS[Index]_HDINPm
PCS[Index]_HDOUTPm
PCS[Index]_REFCLKP
PCS[Index]_VCCOBm
PCS[Index]_VCCIBm
1. When placing switching I/Os around these critical pins that are designed to supply the device with the proper reference or supply voltage,
2. m defines the associated channel in the quad.
care must be given.
Signal Name
2
I/O
I/O
I/O
—
—
O
O
I
I
I
I
Parallel configuration I/O. SPI/SPIm data input. Open drain during configura-
tion.
Serial data input for slave serial mode. SPI/SPIm mode chip select.
High-speed input, negative channel m
High-speed output, negative channel m
Negative Reference Clock Input
High-speed input, positive channel m
High-speed output, positive channel m
Positive Reference Clock Input
Output buffer power supply, channel m (1.2V/1.5)
Input buffer power supply, channel m (1.2V/1.5V)
4-3
Description
LatticeECP3 Family Data Sheet
Pinout Information