LFXP20C-5FN484C Lattice, LFXP20C-5FN484C Datasheet - Page 263

• Manufacturer Part Number: LFXP20C-5FN484C
• Description: IC FPGA 19.7KLUTS 340I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFXP20C-5FN484C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 11-3. Delay Adjustment
PLL Usage in IPexpress
Including sysCLOCK PLLs in a Design
The sysCLOCK PLL capability can be accessed through the IPexpress GUI. The following section describes the
usage of IPexpress.
IPexpress Usage
The LatticeECP/EC and LatticeXP PLL is fully supported in IPexpress in the ispLEVER software. IPexpress allows
the user to define the desired PLL using a simple, easy-to-use GUI. Following definition, a VHDL or Verilog module
that instantiates the desired PLL is created. This module can be included directly in the user’s design.
Figure 11-6 shows the main window when PLL is selected. The only entry required in this window is the module
name. After entering the module name, clicking on “Customize” will open the “Configuration” window as shown in
Figure 11-7.
Note: t
DLY
DDAIZR
= Unit Delay Time = 250 ps (nominal). See the data sheet for the tolerance of this delay
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
DDAMODE = 1: Dynamic Delay Adjustment
Don’t Care
DDAILAG
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
DDAIDEL[2:0]
Don’t Care
11-7
111
110
101
100
011
010
001
000
000
001
010
011
100
101
110
111
sysCLOCK PLL Design and Usage Guide
250ps (nominal)
DELAY 1 t
Lead 8 t
Lead 7 t
Lead 6 t
Lead 5 t
Lead 4 t
Lead 3 t
Lead 2 t
Lead 1 t
Lag 1 t
Lag 2 t
Lag 3 t
Lag 4 t
Lag 5 t
Lag 6 t
Lag 7 t
Lag 8 t
No delay
LatticeECP/EC and LatticeXP
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
DLY
=
Equivalent FDEL Value
DDAMODE = 0
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8