LFXP20C-5F484C Lattice, LFXP20C-5F484C Datasheet - Page 14
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LFXP20C-5F484C
Manufacturer Part Number
LFXP20C-5F484C
Description
IC FPGA 19.7KLUTS 340I/O 484-BGA
Manufacturer
Lattice
Datasheet
1.LFXP3C-3T100C.pdf
(397 pages)
Specifications of LFXP20C-5F484C
Lead Free Status / Rohs Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP20C-5F484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 2-1. LatticeXP Top Level Block Diagram
PFU and PFF Blocks
The core of the LatticeXP devices consists of PFU and PFF blocks. The PFUs can be programmed to perform
Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform
Logic, Arithmetic and ROM functions. Except where necessary, the remainder of the data sheet will use the term
PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
Non-volatile Memory
Programmable
Functional Unit (PFU)
Latch
FF/
LUT4 &
CARRY
D
Programmable I/O Cell
(PIC) includes sysIO
Interface
Slice 0
Latch
FF/
LUT4 &
CARRY
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
LUT4 &
CARRY
D
Routing
Routing
From
2-2
To
Latch
FF/
LUT4 &
CARRY
D
Slice 2
Latch
FF/
CARRY
LUT4 &
D
LatticeXP Family Data Sheet
Latch
FF/
LUT4 &
CARRY
D
Slice 3
Latch
FF/
LUT4 &
CARRY
D
JTAG Port
sysCLOCK PLL
sysMEM Embedded
Block RAM (EBR)
PFF (PFU without
RAM)
Architecture
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