LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 2

• Manufacturer Part Number: LFE2-20E-5FN256I
• Description: IC FPGA 21KLUTS 193I/O 256FPBGA
• Manufacturer: Lattice
• Series: ECP2r

Specifications of LFE2-20E-5FN256I

• Number Of Logic Elements/cells: 21000
• Number Of Labs/clbs: 2625
• Total Ram Bits: 282624
• Number Of I /o: 193
• Number Of Gates: -
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 256-BGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1170; LFE2-20E-5FN256I; Q6411457

LatticeECP2/M architecture
Architecture Overview
The LatticeECP2 family is designed to offer exceptional functionality, performance
and low power. Built with an extremely efficient architecture, these low-cost FPGAs
deliver low power, high-performance DSP blocks, sysMEM embedded RAM blocks,
distributed memory, sysCLOCK PLLs, DDR memory interfaces, source synchronous
interfaces, sysIO buffers, and enhanced configuration capabilities including encryption,
dual-boot and TransFR field updates. The ECP2M devices provide all the features of the
LatticeECP2 family and adds a high performance SERDES block capable of support-
ing many common packet based protocols including PCI Express, Ethernet (1GbE and
SGMII) and related packet protocol standards.
Programmable Function
Unit Blocks (PFU)
The core of LatticeECP2/M devices con-
sists of an array of optimized Program-
mable Functional Units (PFU). The PFUs
can be programmed to perform Logic,
Arithmetic, Distributed RAM and Distrib-
uted ROM functions.
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PFu BLOCk diagraM
Routing
From
Four Slices per PFU
Optimized LUT to Register Ratio
Distributed Memory Supported in
Selected Slices
Each Slice Individually Programmable
Concatenate Slices for Longer
Functions
Concatenate PFUs for Complex
Functions
Carry Chain
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
LUT4
Carry Chain
Slice 3
Slice 2
Slice 1
Slice 0
FF
FF
FF
FF
FF
FF
Routing
To
Enhanced Configuration
Each LatticeECP2/M device can be con-
figured using:
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The configuration interface has a number
of enhanced features, including:
Dual Boot Operation – Supports the
storage of multiple configurations in SPI
memory, adding flexibility and reliability,
particularly for systems that require field
updates.
Bitstream Encryption – LatticeECP2/M
devices provide on-chip, non-volatile key
storage to support decryption of a 128-
bit AES encrypted bitstream, securing
designs and preventing design piracy.
TransFR I/O – LatticeECP2/M devices
feature TransFR I/O that allows I/O states
to be frozen during device configuration.
This allows device field updates with a
minimum of system downtime.
A Low-Cost SPI Flash Memory
The LatticeECP2/M JTAG Port
The LatticeECP2/M Serial or Parallel
Microprocessor Port
Sector 0
Sector 1
Configuration Memory
Flash (Configuration 2)
Configuration
(Configuration 1)
LatticeECP2/M
Logic – SRAM
SPI Configuration
128-bit AES
Memory
Encrypted
[
[
Bitstream
Upgrade
FLASH
Memory
Config. A
Config. B
Read
Control
Data
LatticeECP2/M
128-bit Key
Decryption
Engine
Configuration Memory
LatticeECP2/M
Flash (Configuration 2)
LatticeECP2/M
(Configuration 2)
Logic – SRAM
FPGA
Logic
Flexible sysIO
Buffers support
LVCMOS, HSTL,
SSTL, LVDS and
more.
LatticeECP2M
Block Diagram
High-Speed sysDSP Blocks
LatticeECP2/M devices include up to
42 high-performance sysDSP blocks per
device. sysDSP blocks are optimized for
processing intensive applications and al-
low designers to quickly implement DSP
functions. Each sysDSP block provides:
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Programmable
Function Unit
(PFU)
perform Logic,
Arithmetic,
Distributed RAM
and Distributed
ROM functions.
sysCLOCK PLLs
& DLLs for clock
management.
Configurable Multiplier Widths:
Programmable Addition, Subtraction,
and Accumulate Modes
Programmable Pipelining – Input,
Intermediate and Output
375MHz Performance
On-Chip
Oscillator
• One 36x36
• Four 18x18
• Eight 9x9
Advanced Configuration Logic supports
dual boot, encryption, and TransFR I/O.
Low-cost LatticeECP2M de-
vices offer more of the best
with 3.125Gbps SERDES,
up to 95K LUTs at
under 0.35W static power,
533Mbps DDR2 interface,
dual boot support, and up to
168 18x18 multipliers.