LFEC15E-3FN484C Lattice, LFEC15E-3FN484C Datasheet - Page 32

• Manufacturer Part Number: LFEC15E-3FN484C
• Description: IC FPGA 10.2KLUTS 288I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFEC15E-3FN484C

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 220-1231

Lattice Semiconductor
Figure 2-34. LatticeECP/EC Banks
LatticeECP/EC devices contain two types of sysI/O buffer pairs.
1. Top and Bottom sysI/O Buffer Pairs (Single-Ended Outputs Only)
2. Left and Right sysI/O Buffer Pairs (Differential and Single-Ended Outputs)
The sysI/O buffer pairs in the top and bottom banks of the device consist of two single-ended output drivers
and two sets of single-ended input buffers (both ratioed and referenced). The referenced input buffer can also
be configured as a differential input.
The two pads in the pair are described as “true” and “comp”, where the true pad is associated with the positive
side of the differential input buffer and the comp (complementary) pad is associated with the negative side of
the differential input buffer.
Only the I/Os on the top and bottom banks have programmable PCI clamps. These I/O banks also support hot
socketing with IDK less than 1mA. Note that the PCI clamp is enabled after V
operating levels and the device has been configured.
The sysI/O buffer pairs in the left and right banks of the device consist of two single-ended output drivers, two
sets of single-ended input buffers (both ratioed and referenced) and one differential output driver. The refer-
enced input buffer can also be configured as a differential input. In these banks the two pads in the pair are
described as “true” and “comp”, where the true pad is associated with the positive side of the differential I/O,
and the comp (complementary) pad is associated with the negative side of the differential I/O.
Only the left and right banks have LVDS differential output drivers. See the I
rent during power-up.
V
V
V
V
V
V
GND
GND
REF1(7)
REF2(7)
CCIO7
CCIO6
REF2(6)
REF1(6)
Bank 0
Bank 5
BOTTOM
2-29
TOP
Bank 1
Bank 4
LatticeECP/EC Family Data Sheet
DK
CC
specification for I/O leakage cur-
, V
V
V
V
V
V
V
GND
GND
CCAUX
REF1(2)
REF2(2)
REF2(3)
REF1(3)
CCIO2
CCIO3
and V
CCIO
Architecture
are at valid