M25PE40-VMW6G Micron Technology Inc, M25PE40-VMW6G Datasheet - Page 14
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
M25PE40-VMW6G
Manufacturer Part Number
M25PE40-VMW6G
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25PE40-VMW6G.pdf
(62 pages)
Specifications of M25PE40-VMW6G
Cell Type
NOR
Density
4Mb
Access Time (max)
15ns
Interface Type
Serial (SPI)
Boot Type
Not Required
Address Bus
1b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
512K
Supply Current
8mA
Mounting
Surface Mount
Pin Count
8
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Operating features
4.7
4.8
4.8.1
14/62
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by using specific instructions. See
for a detailed description of the Status Register bits.
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
features the following data protection mechanisms:
Protocol-related protections
Power On Reset and an internal timer (t
changes while the power supply is outside the operating specification.
Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
–
–
–
The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For
the specific cases of Program and Write cycles, the designer should refer to
Section 6.5: Write Status Register
Section 6.10: Page Program
Erase
a Reset Low
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
Power-up
Reset (Reset) driven Low
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Write to Lock Register (WRLR) instruction completion
Page Erase (PE) instruction completion
Subsector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
(SE),
Section 6.13: Subsector Erase
pulse.
(PP),
Section 6.12: Page Erase
(WRSR),
PUW
Section 6.4: Read Status Register (RDSR)
) can provide protection against inadvertent
(SSE), and to
Section 6.9: Page Write
Table 12: Device status after
(PE),
Section 6.14: Sector
(PW),
M25PE40