M25P64-VME6TG Micron Technology Inc, M25P64-VME6TG Datasheet - Page 53

• Manufacturer Part Number: M25P64-VME6TG
• Manufacturer: Micron Technology Inc

Specifications of M25P64-VME6TG

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VDFPN EP
• Program/erase Volt (typ): 8.5 to 9.5V
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 8M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

14
Revision history
Table 22.
15-May-2003
02-Sep-2003
19-Sep-2003
17-Dec-2003
15-Nov-2004
23-Dec-2005
07-Sep-2006
24-Feb-2005
16-Feb-2006
28-Apr-2003
20-Jun-2003
19-Jan-2007
18-Jul-2003
Date
Document revision history
Revision
0.3
0.4
0.5
0.6
0.7
1.0
2.0
3.0
4.0
0.1
0.2
5
6
Target Specification Document written in brief form
Target Specification Document written in full
8x6 MLP8 and SO16(300 mil) packages added
t
Voltage supply range changed
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added
Value of t
removed.
Document status promoted from Target Specification to Preliminary Data.
8x6 MLP8 package added. Minor wording changes.
Deep Power-Down mode removed from datasheet
Electronic Signature (RES) instruction sequence and data-out sequence
modified and tRES1 and tRES2 removed from
characteristics). SO16 Wide package specifications updated. End timing
line of t
the corresponding instructions in the
Updated Page Program (PP) instructions in
Program (PP)
Fast Program/Erase mode
Program/Erase mode in
changed to W/V
(W/VPP)
removed under
t
timing
All packages are RoHS compliant.
Document status promoted from Preliminary Data to full Datasheet
status.
VDFPN8 (MLP8) package specifications updated (see
Package
Figure 4: Bus master and memory devices on the SPI bus
I
Hardware Write Protection feature added to
VCC supply voltage
Figure 4: Bus master and memory devices on the SPI bus
explanatory paragraph added.
At Power-up
V
ratings. Small text changes.
Note 1
Package No lead, 8 × 6 mm, package mechanical
PP
VPPHSL
CC1
IO
, t
max modified and T
SE
maximum value updated in
inserted.
SHQZ
added to
and t
added to
VSL
description). Note
mechanical).
BE
(min) V
modified in
The Write In Progress (WIP) bit is
and
revised
Plating
PP
Table 18: VDFPN8 (MLP8) 8-lead Very thin Dual Flat
Table 16: AC characteristics
. (see
Table 16: AC
WI
and
, t
Technology.
LEAD
PP
Write Protect/Enhanced Program supply voltage
Figure 24: Output
Power-up and Power-down
VSS ground
(typ) and t
added and Power-up specified for Fast
2
added in
inserted below
Changes
characteristics.
Table 14: DC
BE
Instructions
descriptions added.
Table 9: Absolute maximum
(typ) changed. MLP8 package
timing. Figures moved below
Page
Features on page
Figure 26
characteristics.
and
Table 16: AC
reset.
section.
Programming,
(Figure 18: Read
Figure 25: VPPH
data.
section. W pin
Section 11:
Blank option
modified.
updated and
1.
Page
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