CY7C25702KV18-550BZXI Cypress Semiconductor Corp, CY7C25702KV18-550BZXI Datasheet - Page 21

• Manufacturer Part Number: CY7C25702KV18-550BZXI
• Description: IC SRAM DDR-II+ CIO-ODT 165FBGA
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C25702KV18-550BZXI

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................- 65 C to +150 C
Ambient Temperature with Power Applied.-55 C to +125 C
Supply Voltage on V
Supply Voltage on V
DC Applied to Outputs in High Z ..........-0.5V to V
DC Input Voltage
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015)... >2,001V
Latch up Current..................................................... >200 mA
Operating Range
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range
Notes
Document Number: 001-66483 Rev. **
V
V
V
V
V
V
V
V
I
I
V
17. Power up: assumes a linear ramp from 0V to V
18. Outputs are impedance controlled. I
19. Outputs are impedance controlled. I
20. V
Commercial
Industrial
X
OZ
Parameter
DD
DDQ
OH
OL
OH(LOW)
OL(LOW)
IH
IL
REF
Range
REF
(min) = 0.68V or 0.46V
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Input Reference Voltage
[13]
Temperature (T
-40°C to +85°C
0 C to +70 C
DD
DDQ
...............................-0.5V to V
Description
Ambient
Relative to GND ........ -0.5V to +2.9V
Relative to GND ....... -0.5V to +V
DDQ
[14]
, whichever is larger, V
OH
OL
= (V
= -(V
A
)
DDQ
DDQ
[20]
1.8 ± 0.1V
DD
/2)/(RQ/5) for values of 175 < RQ < 350.
V
/2)/(RQ/5) for values of 175 < RQ < 350.
(min) within 200 ms. During this time V
DD
Note 18
Note 19
I
I
GND  V
GND  V
Typical Value = 0.75V
OH
OL
[17]
REF
= 0.1 mA, Nominal Impedance
=0.1 mA, Nominal Impedance
(max) = 0.95V or 0.54V
DDQ
DD
I
I
V
1.4V to
 V
 V
+ 0.3V
+ 0.3V
DDQ
V
Test Conditions
DD
DDQ
DDQ,
DD
[17]
Output Disabled
DDQ
Neutron Soft Error Immunity
Parameter
LSBU
LMBU
SEL
* No LMBU or SEL events occurred during testing; this column
represents a statistical 
more details refer to Application Note AN 54908 “Accelerated
Neutron SER Testing and Calculation of Terrestrial Failure Rates”
, whichever is smaller.
IH
CY7C25662KV18, CY7C25772KV18
CY7C25682KV18, CY7C25702KV18
< V
DD
and V
Single Event
Description
Single-Bit
Latch up
DDQ
Multi-Bit
Logical
Logical
Upsets
Upsets
V
V
< V
DDQ
DDQ
V
V
DD
DDQ
REF
-0.15
0.68
.
Min
V
2
1.7
1.4
/2 – 0.12
/2 – 0.12
2
2
, 95% confidence limit calculation. For
SS
+ 0.1
– 0.2
Conditions
25°C
25°C
85°C
Test
0.75
Typ
1.8
1.5
V
V
Typ
197
V
DDQ
DDQ
0
0
V
DDQ
REF
V
Max
0.95
V
/2 + 0.12
/2 + 0.12
1.9
0.2
DDQ
DD
2
2
+ 0.15
Max*
– 0.1
0.01
Page 21 of 29
216
0.1
Unit
FIT/
FIT/
FIT/
Dev
Mb
Mb
Unit
A
A
V
V
V
V
V
V
V
V
V
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