NOIL1SM4000A-GDC ON Semiconductor, NOIL1SM4000A-GDC Datasheet - Page 7

• Manufacturer Part Number: NOIL1SM4000A-GDC
• Description: LUPA4000 MONO PGA127
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM4000A-GDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Pixel Array Drivers
signals The driving on system level is easy and flexible; the
maximum currents applied to the sensor are also controlled
on-chip. This means that the charging on sensor level is
fixed; the sensor cannot be overdriven externally. The
operation of the on-chip drivers is explained in Timing and
Readout of Image Sensor on page 13.
Column Amplifiers
dissipation and minimum loss of signal, resulting in multiple
biasing signals.
‘voltage-averaging’ feature. In the voltage-averaging mode,
the voltage average between two columns is read out. In this
mode, only 2:1 pixels must be read out.
external digital signal called voltage-averaging is required
in combination with a bit from the SPI.
Analog-to-Digital Converter
nominally at 10 Msamples/s. The ADC block is electrically
separated from the image sensor. The inputs of the ADC
must be tied externally to the outputs of the output
amplifiers. If the internal ADC is not used, then the power
supply pins to the ADC and the I/Os must be grounded.
to sustain the 66 Mpixel/sec provided by the output
amplifier when run at full speed.
samples the odd columns. Although the input range of the
ADC is between 1 V and 2 V and the output range of the
The image sensor has on-chip drivers for the pixel array
The column amplifiers are designed for minimum power
The
To achieve the voltage-averaging mode, an additional
The LUPA4000 has two 10-bit flash ADCs running
Even in this configuration, the internal ADCs are not able
One ADC samples the even columns and the second ADC
column
amplifiers
have
an
integrated
Figure 6. ADC Timing
http://onsemi.com
7
analog signal is between 0.3 V and 1.3 V, the analog output
and digital input may be tied to each other directly. This is
possible because there is an on-chip level-shifter located in
front of the ADC to lift up the analog signal to the ADC
range.
Errata for Internal ADCs
ADC clock, not operational at system clock. No fix is
intended to resolve this limitation.
1. The internal ADC range is typically 50 mW lower than the external
ADC Timing
ADC_CLOCK, but it takes two clock cycles before this
pixel data is at the output of the ADC. This pipeline delay is
shown in Figure 6.
Table 1. ADC SPECIFICATIONS
Input range
Quantization
Normal data rate
Differential nonlinearity (DNL) -
linear conversion mode
Integral nonlinearity (INL) -
linear conversion mode
Input capacitance
Power dissipation at 33 MHz
Conversion law
Use external ADCs due to the limitation of the internal
The ADC converts the pixel data on the falling edge of the
applied ADC_VHIGH and ADC_VLOW voltages due to voltage
drops over parasitic internal resistors in the ADC.
Parameter
1 V to 2 V (Note 1)
10 bits
10 Msamples/s
Typ. < 0.4 LSB RMS
Typ. < 3.5 LSB
< 2 pF
50 mW
Linear/Gamma−corrected
Specification