LTC1391IGN Linear Technology, LTC1391IGN Datasheet - Page 6

• Manufacturer Part Number: LTC1391IGN
• Description: IC MULTIPLEXER 8X1 16SSOP
• Manufacturer: Linear Technology

Specifications of LTC1391IGN

• Function: Multiplexer
• Circuit: 1 x 8:1
• On-state Resistance: 75 Ohm
• Voltage Supply Source: Dual Supply
• Voltage - Supply, Single/dual (±): ±2.7 V ~ 5 V
• Current - Supply: 15µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SSOP (0.150", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APPLICATIONS
LTC1391
Multiplexer Operation
Figure 1 shows the block diagram of the components
within the LTC1391 required for MUX operation. The
LTC1391 uses D
select input, CS, to switch on the selected channel as
shown in Figure 2.
When CS is high, the input data on the D
into the 4-bit shift register on the rising clock edge. The
input data consists of the “EN” bit and a string of three bits
for channel selection. If “EN” bit is logic high as illustrated
in the first input data sequence, it enables the selected
channel. After the clocking in of the last channel selection
bit B0, the CS pin must be pulled low before the next rising
clock edge to ensure correct operation. Once CS is pulled
low, the previously selected channel is switched off to
ensure a break-before-make interval. After a delay of t
the selected channel is switched on allowing signal trans-
mission. The selected channel remains on until the next
falling edge of CS. After a delay of t
terminates the analog signal transmission and allows the
6
Figure 1. Simplified Block Diagram of the MUX Operation
ANY ANALOG
CLK
D
CS
IN
INPUT
CLK
ANALOG INPUTS
D
CS
IN
D
IN
(S0 TO S7)
CONTROL
to select the active channel and the chip
LOGIC
U
HIGH
EN
INFORMATION
U
B2
4-BIT SHIFT
REGISTER
B1
BLOCK
MUX
W
B0
OFF
IN
, the LTC1391
pin is latched
ANALOG
OUTPUT (D)
t
ON
Figure 2. Multiplexer Operation
1391 • F01
U
ON
,
selection of next channel. If the “EN” bit is logic low, as
illustrated in the second data sequence, it disables all
channels and there will be no analog signal transmission.
Table 1 shows the various bit combinations for channel
selection.
Table 1. Logic Table for Channel Selection
Digital Data Transfer Operation
The block diagram of Figure 3 shows the components
within the LTC1391 required for serial data transfer. When
CS is held high, data is fed into the 4-bit shift register and
then shifted to D
rising edge of the clock as shown in Figure 4. The last four
ACTIVE CHANNEL
All Off
CLK
D
EN LO
S0
S1
S2
S3
S4
S5
S6
S7
CS
IN
Figure 3. Simplified Block Diagram of the
Digital Data Transfer Operation
B2
OUT
CONTROL
LOGIC
B1
. Data appears at D
EN
t
0
1
1
1
1
1
1
1
1
OFF
B0
4-BIT SHIFT
REGISTER
B2
X
0
0
0
0
1
1
1
1
OUT
B1
X
0
0
1
1
0
0
1
1
after the fourth
1391 F03
D
OUT
1391 • F02
sn1391 1391fas
BO
X
0
1
0
1
0
1
0
1