ADC101S021EVAL National Semiconductor, ADC101S021EVAL Datasheet - Page 11

• Manufacturer Part Number: ADC101S021EVAL
• Manufacturer: National Semiconductor

Specifications of ADC101S021EVAL

• Lead Free Status / Rohs Status: Not Compliant

3.0 ADC101S021 TRANSFER FUNCTION
The output format of the ADC101S021 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC101S021 is V
The ideal transfer characteristic is shown in Figure 5. The
transition from an output code of 00 0000 0000 to a code of
00 0000 0001 is at 1/2 LSB, or a voltage of V
code transitions occur at steps of one LSB.
4.0 TYPICAL APPLICATION CIRCUIT
A typical application of the ADC101S021 is shown
in Figure 6. Power is provided in this example by the National
Semiconductor LP2950 low-dropout voltage regulator, avail-
able in a variety of fixed and adjustable output voltages. The
power supply pin is bypassed with a capacitor network locat-
ed close to the ADC101S021. Because the reference for the
ADC101S021 is the supply voltage, any noise on the supply
will degrade device noise performance. To keep noise off the
supply, use a dedicated linear regulator for this device, or
provide sufficient decoupling from other circuitry to keep noise
off
ADC101S021's low power requirements, it is also possible to
use a precision reference as a power supply to maximize per-
formance. The three-wire interface is shown connected to a
microprocessor or DSP.
5.0 ANALOG INPUTS
An equivalent circuit for the ADC101S021's input is shown in
Figure 7. Diodes D1 and D2 provide ESD protection for the
analog inputs. At no time should the analog input go beyond
the
FIGURE 5. Ideal Transfer Characteristic
FIGURE 6. Typical Application Circuit
ADC101S021
supply
pin.
Because
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the
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begin conducting, which could result in erratic operation. For
this reason, the ESD diodes should not be used to clamp the
input signal.
The capacitor C1 in Figure 7 has a typical value of 4 pF, and
is mainly the package pin capacitance. Resistor R1 is the on
resistance of the track / hold switch, and is typically 500 ohms.
Capacitor C2 is the ADC101S021 sampling capacitor and is
typically 26 pF. The ADC101S021 will deliver best perfor-
mance when driven by a low-impedance source to eliminate
distortion caused by the charging of the sampling capaci-
tance. This is especially important when using the AD-
C101S021 to sample AC signals. Also important when
sampling dynamic signals is an anti-aliasing filter
6.0 DIGITAL INPUTS AND OUTPUTS
The ADC101S021 digital inputs (SCLK and CS) are not lim-
ited by the same maximum ratings as the analog inputs. The
digital input pins are instead limited to +5.25V with respect to
GND, regardless of V
ADC101S021 to be interfaced with a wide range of logic lev-
els, independent of the supply voltage.
7.0 MODES OF OPERATION
The ADC101S021 has two possible modes of operation: nor-
mal mode, and shutdown mode. The ADC101S021 enters
normal mode (and a conversion process is begun) when CS
is pulled low. The device will enter shutdown mode if CS is
pulled high before the tenth falling edge of SCLK after CS is
pulled low, or will stay in normal mode if CS remains low.
Once in shutdown mode, the device will stay there until CS is
brought low again. By varying the ratio of time spent in the
normal and shutdown modes, a system may trade-off
throughput for power consumption, with a sample rate as low
as zero.
7.1 Normal Mode
The fastest possible throughput is obtained by leaving the
ADC101S021 in normal mode at all times, so there are no
power-up delays. To keep the device in normal mode contin-
uously, CS must be kept low until after the 10th falling edge
of SCLK after the start of a conversion (remember that a con-
version is initiated by bringing CS low).
If CS is brought high after the 10th falling edge, but before the
16th falling edge, the device will remain in normal mode, but
the current conversion will be aborted, and SDATA will return
to TRI-STATE (truncating the output word).
Sixteen SCLK cycles are required to read all of a conversion
word from the device. After sixteen SCLK cycles have
elapsed, CS may be idled either high or low until the next
conversion. If CS is idled low, it must be brought high again
A
+ 300 mV) or (GND − 300 mV), as these ESD diodes will
FIGURE 7. Equivalent Input Circuit
A
, the supply voltage. This allows the
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