SDKZSPF LSI, SDKZSPF Datasheet - Page 162

• Manufacturer Part Number: SDKZSPF
• Manufacturer: LSI

Specifications of SDKZSPF

• Lead Free Status / Rohs Status: Supplier Unconfirmed

8-20
ZSP SDK Cycle-Accurate Simulator
Copyright © 1999-2003 by LSI Logic Corporation. All rights reserved.
cycle: Cycle count that the register is modified.
seqID: Unique ascending sequence number for each instruction.
PC: Address of instruction in memory.
Instruction: Disassembled instruction.
Register: Architecture register name.
Direction: Direction for a discontinuity instruction such as branch or
conditional execution. Direction is either forward or backward, and
the result is either taken or not taken.
+=+=: A register is modified without any associated instruction such
as when an interrupt is taken or a timer enable mode.
For example:
<13> (1) 0x000002 6200 mov %fmode, r0 !
Instruction mov %fmode, r0 modifies %fmode to value 0x0014 at
cycle 13.
mem
Displays address and data for any memory location which is
updated. Information is generated in the cycle in which the write
occurs. This option is a subset of ‘enable trace write’ because it does
not display register updates.
<cycle> (seqID) PC Opcode Instruction [Memory
Address]=Value
For example:
<99> (255) 0x00006d 1884 stu r0, a4, 1
! [0x00000024]=0x9966
Instruction stu r0, a4,1 writes value 0x9966 to memory location
0x24 at cycle 99.
icache
Displays the entire instruction cache in every cycle. See show
icache command for output description. This command is valid only
for G2.
pipe
Displays the entire pipeline in every cycle. See show pipe command
for output description
fmode=0x0014