SE7320VP2BPP Intel, SE7320VP2BPP Datasheet - Page 43
![no-image](/images/manufacturer_photos/0/3/336/intel_sml.jpg)
SE7320VP2BPP
Manufacturer Part Number
SE7320VP2BPP
Description
Manufacturer
Intel
Datasheet
1.SE7320VP2BPP.pdf
(185 pages)
Specifications of SE7320VP2BPP
Lead Free Status / Rohs Status
Not Compliant
- Current page: 43 of 185
- Download datasheet (2Mb)
Intel® Server Board SE7320VP2
3.4.2
The Server Board SE7320VP2 interrupt architecture accommodates both PC-compatible PIC
mode and APIC mode interrupts through use of the integrated I/O APICs in the 6300ESB ICH.
3.4.2.1
For PC-compatible mode, the 6300ESB ICH provides two 82C59-compatible interrupt
controllers. The two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the
primary interrupt controller (standard PC configuration). A single interrupt signal is presented to
the processors, to which only one processor will respond for servicing. The 6300ESB ICH
contains configuration registers that define which interrupt source logically maps to I/O APIC
INTx pins.
Both PCI and IRQ types of interrupts are handled by the 6300ESB ICH. The 6300ESB ICH
translates these to the APIC bus. The numbers in the table below indicate the 6300ESB ICH
PCI interrupt input pin to which the associated device interrupt (INTA, INTB, INTC, INTD) is
connected. The 6300ESB ICH I/O APIC exists on the I/O APIC bus with the processors.
3.4.2.2
For APIC mode, the Server Board SE7320VP2 interrupt architecture incorporates two Intel I/O
APIC devices to manage and broadcast interrupts to local APICs in each processor. The Intel
I/O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA
compatibility interrupts IRQ(0-15). When an interrupt occurs, a message corresponding to the
interrupt is sent across a three-wire serial interface to the local APICs. The APIC bus minimizes
interrupt latency time for compatibility interrupt sources. The I/O APICs can also supply greater
than 16 interrupt levels to the processor(s). This APIC bus consists of an APIC clock and two
bidirectional data lines.
Revision 2.1
Intel
Video
SIO
Legacy IDE (Primary)
Legacy IDE (Secondary)
FH Riser TCK and TCO
P64-A Slot 1
P64-A Slot 2
P64-A Slot 3
®
82541PI NIC
Interrupt Routing
Legacy Interrupt Routing
APIC Interrupt Routing
Interrupt
Table 10. PCI Interrupt Routing/Sharing
Intel order number C91056-002
ICH_PIRQA
ICH_PIRQB
ICH_SERIRQ
ICH_PIRQ14
ICH_PIRQ15
P64A_IRQ0
P64A_IRQ0
P64A_IRQ1
P64A_IRQ2
INT A
P64A_IRQ1
P64A_IRQ2
P64A_IRQ3
P64A_IRQ1
INT B
P64A_IRQ2
P64A_IRQ2
P64A_IRQ3
P64A_IRQ0
INT C
Functional Architecture
P64A_IRQ3
P64A_IRQ3
P64A_IRQ0
P64A_IRQ1
INT D
43