SSDSA2CW080G310 Intel, SSDSA2CW080G310 Datasheet - Page 15

• Manufacturer Part Number: SSDSA2CW080G310
• Manufacturer: Intel

Specifications of SSDSA2CW080G310

• Lead Free Status / Rohs Status: Compliant

Intel
Table 11.
Notes:
1.
2.
3.
4.
5.
6.
7.
March 2011
Order Number: 325152-001US
®
P12
Solid-State Drive 320 Series
P4
P7
P8
P9
Pin
P10
P11
P13
P14
P15
All pins are in a single row, with a 1.27 mm (0.050-inch) pitch.
Pins P1, P2 and P3 are connected together, although they are not connected internally to the device. The host may put
3.3 V on these pins.
The mating sequence is:
Ground connectors P4 and P12 may contact before the other 1st mate pins in both the power and signal connectors to
discharge ESD in a suitably configured backplane connector.
Power pins P7, P8, and P9 are internally connected to one another within the device.
The host may ground P11 if it is not used for Device Activity Signal (DAS).
Pins P13, P14 and P15 are connected together, although they are not connected internally to the device. The host may put
12 V on these pins.
P1
P2
P3
P5
P6
•
•
3,4
3,5
3,5
3,5
3, 4
2
2
2
3
3
1
3
6
7
7
7
the ground pins P4-P6, P10, P12 and the 5V power pin P7.
the signal pins and the rest of the 5V power pins P8-P9.
Serial ATA Power Pin Definitions — 2.5-inch Form Factor
Not connected
Not connected
Not connected
Ground
Ground
Ground
V
V
V
Ground
DAS
Ground
V
V
V
5
5
5
12
12
12
Function
(3.3 V Power)
(3.3 V Power)
(3.3 V Power; pre-charge)
5 V Power
5 V Power
5 V Power
Device Activity Signal
12 V Power; not used
12 V Power; not used
12 V Power; not used
Definition
Intel
®
Solid-State Drive 320 Series
Product Specification
Mating Order
2nd Mate
2nd Mate
2nd Mate
2nd Mate
2nd Mate
2nd Mate
1st Mate
1st Mate
1st Mate
1st Mate
1st Mate
1st Mate
1st Mate
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