M25PX64-VMF6TP Micron Technology Inc, M25PX64-VMF6TP Datasheet - Page 9
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M25PX64-VMF6TP
Manufacturer Part Number
M25PX64-VMF6TP
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25PX64-VMF6TP.pdf
(70 pages)
Specifications of M25PX64-VMF6TP
Cell Type
NOR
Density
64Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Address Bus
24b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
8M
Supply Current
12mA
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25PX64-VMF6TP
Manufacturer:
NUMONYX
Quantity:
5 100
Part Number:
M25PX64-VMF6TP
Manufacturer:
ST
Quantity:
20 000
2
2.1
2.2
2.3
2.4
2.5
Signal descriptions
Serial data output (DQ1)
This output signal is used to transfer data serially out of the device. Data are shifted out on
the falling edge of Serial Clock (C).
During the dual input fast program (DIFP) instruction, pin DQ1 is used as an input. It is
latched on the rising edge of the Serial Clock (C).
Serial data input (DQ0)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
During the dual output fast read (DOFR) instruction, pin DQ0 is used as an output. Data are
shifted out on the falling edge of the Serial Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at serial data input (DQ0) are latched on the rising edge of Serial Clock (C). Data on
serial data output (DQ1) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and serial data output (DQ1) is at
high impedance. Unless an internal program, erase or write status register cycle is in
progress, the device will be in the standby power mode (this is not the deep power-down
mode). Driving Chip Select (S) Low enables the device, placing it in the active power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the hold condition, the serial data output (DQ1) is high impedance, and serial data
input (DQ0) and Serial Clock (C) are don’t care.
To start the hold condition, the device must be selected, with Chip Select (S) driven Low.
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