DS1990R-F5 Maxim Integrated Products, DS1990R-F5 Datasheet - Page 4

• Manufacturer Part Number: DS1990R-F5
• Description: Serial Number Registration
• Manufacturer: Maxim Integrated Products

Specifications of DS1990R-F5

• Lead Free Status / Rohs Status: No

Figure 2. 64-BIT LASERED ROM
Figure 3. 1-WIRE CRC GENERATOR
1-Wire BUS SYSTEM
The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances the DS1990R
is a slave device. The bus master is typically a microcontroller or PC. For small configurations the 1-Wire
communication signals can be generated under software control using a single port pin. Alternatively, the DS2480B
1-Wire line driver chip or serial port adapters based on this chip (DS9097U series) can be used. This simplifies the
hardware design and frees the microprocessor from responding in real-time. The discussion of this bus system is
broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types
and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that
are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer
to Chapter 4 of the Book of DS19xx iButton Standards.
HARDWARE CONFIGURATION
The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at
the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open drain or tri-state
outputs. The 1-Wire port of the DS1990R is open-drain with an internal circuit equivalent to that shown in Figure 4.
A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has a
maximum data rate of 16.3kbps. The value of the pullup resistor primarily depends on the network size and load
conditions. For most applications the optimal value of the pullup resistor is approximately 2.2kW. The idle state for
the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. If this does not occur and the bus is left low for more than 120µs, one or more
devices on the bus may be reset.
TRANSACTION SEQUENCE
The protocol for accessing the DS1990R through the 1-Wire port is as follows:
§
§
X
Initialization
ROM Function Command
0
STAGE
1
st
MSB
MSB
CRC CODE
X
1
8-BIT
STAGE
2
nd
LSB
X
2
STAGE
3
rd
MSB
X
3
STAGE
4
th
POLYNOMIAL = X
48-BIT SERIAL NUMBER
X
4 of 8
4
STAGE
8
5
+ X
th
5
+ X
4
+ 1
X
5
STAGE
LSB
6
th
INPUT DATA
X
6
MSB
STAGE
8-BIT FAMILY
CODE (01h)
7
th
X
7
STAGE
LSB
8
LSB
th
X
8