DS2408S+ Maxim Integrated Products, DS2408S+ Datasheet - Page 25

• Manufacturer Part Number: DS2408S+
• Description: PROM 1-Wire 8-Ch Addressable Switch
• Manufacturer: Maxim Integrated Products

Specifications of DS2408S+

• Lead Free Status / Rohs Status: Details

Read-Data Time Slot
Slave-to-Master
A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below
V
DS2408 starts pulling the data line low; its internal timing generator determines when this pulldown ends
and the voltage starts rising again. When responding with a 1, the DS2408 does not hold the data line low
at all, and the voltage starts rising as soon as t
The sum of t
side define the master sampling window (t
from the data line. For most reliable communication, t
should read close to but no later than t
t
time slot.
Improved Network Behavior
In a 1-Wire environment, line termination is possible only during transients controlled by the bus master
(1-Wire driver). 1-Wire networks therefore are susceptible to noise of various origins. Depending on the
physical size and topology of the network, reflections from end points and branch points can add up or
cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire
communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal
glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization
with the master and, as a consequence, result in a Search ROM command coming to a dead end or cause a
device level command to abort. For better performance in network applications, the DS2408 uses a new
1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected
by the slave device itself.
The 1-Wire front end of the DS2408 differs from traditional slave devices in four characteristics.
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the
2) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a
SLOT
TLMIN
line impedance than a digitally switched transistor, converting the high-frequency ringing known
from traditional devices into a smoother low-bandwidth transition. The slew rate control is specified
by the parameter t
time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply
at overdrive speed.
is expired. This guarantees sufficient recovery time t
until the read low time t
V
IHMASTER
V
RL
V
ILMAX
V
V
PUP
0V
+ d (rise time) on one side and the internal timing generator of the DS2408 on the other
TH
TL
t
F
FPD
RESISTOR
, which has different values for standard and overdrive speed.
t
RL
RL
d
has expired. During the t
MSRMAX
t
Sampling
SPDMIN
Window
Master
MSRMIN
t
RL
. After reading from the data line, the master must wait until
MSR
is over.
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to t
MASTER
RL
MSRMAX
t
SPDMAX
should be as short as permissible and the master
REC
RL
) in which the master must perform a read
for the DS2408 to get ready for the next
window, when responding with a 0, the
t
SLOT
t
REC
DS2408