DVK90129 Melexis Inc, DVK90129 Datasheet - Page 32

• Manufacturer Part Number: DVK90129
• Description: DEVELOPMENT KIT MLX90129
• Manufacturer: Melexis Inc
• Series: -r
• Type: Development kitr

Specifications of DVK90129

• Contents: Board, Proxima RF™ Desktop Reader
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: MLX90129

Core Transaction Arbiter
Part of the Digital Controller, the “Core transaction arbiter” deals with several tasks:
Memory access conflicts between SPI, RFID and DMA
The two communication channels, SPI and RFID, and the internal DMA (Direct Memory Access) are able to
access the memories (EEPROM, registers…) or the sensor ADC buffer, at the same time. The potential
access conflicts are managed by the Core transaction arbiter. A DMA transaction may be interrupted by a
RFID or a SPI starting communication. The RFID (resp. SPI) transaction cannot be interrupted by a starting
SPI (resp. RFID) communication, or a DMA operation. In each case, the current transaction is completed.
The priority order is the following:
Management of two subsequent transactions, from the same communication channel:
A transaction initiated via RFID or SPI should be completed before starting a new one. If a request is sent to
the MLX90129 by a SPI master, or by a RFID base-station, and the current transaction is not completed, then
it is dealt differently depending on its nature:
_ the reading of the Core interrupt / status word is allowed at any time and its content is sent in the response.
_ the reading of a memory (a register or an EEPROM word) is denied and an error-message response may
be sent. For the SPI, it contains 0xFFFF. For the RFID, the content of the response is described in the
standard protocol.
_ if the request is not understood, it is not processed, and a flag is set in the Core interrupt / status word .
This flag is reset once it has been read.
The Core interrupt / status word (Internal device #01)
The Core transaction arbiter updates its Core interrupt / status word at each transaction. This status word is
read-only and contains some information about the processing of the incoming request. It indicates:
_ whether the system is busy or not
_ whether the last request has been processed
_ whether the processing of the last request has failed
_ the source(s) of the interrupt, if the interrupt signal on pin IRQ is asserted ‘1’.
One Core interrupt / status word is associated to each communication way (SPI or RFID). Its content is
explained in the chapters dedicated to RFID and to SPI.
The Core Control Word (Internal device #00)
The Core transaction arbiter updates its Core control word at each transaction. This status word is read/write
and contains the settings used to control the interrupt signal IRQ, and the potential interrupts from other
communication channel. One Core control word is associated to each communication way (SPI or RFID). Its
content is explained in the chapters dedicated to RFID and to SPI.
3901090129
Rev 007
8.3 Management of communication conflicts
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•
•
Grant or deny accesses of the communication interfaces to the different memories
Manage the interrupts
Update the status of the current operations
1. SPI (highest priority)
2. RFID
3. DMA
13.56MHZ SENSOR TAG / DATALOGGER IC
Page 32 of 56
MLX90129
Data Sheet
March 2011