83336-0 Peregrine Semiconductor, 83336-0 Datasheet - Page 3

• Manufacturer Part Number: 83336-0
• Description: KIT EVAL FOR 83336 PLL INTEGER-N
• Manufacturer: Peregrine Semiconductor
• Series: -r

Specifications of 83336-0

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 83336-00

PE83336
Product Specification
Table 1. Pin Descriptions (continued)
Document No. 70-0137-02 │ www.psemi.com
(44-lead
Pin No.
CQFJ)
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Hop_WR
Sdata
D
M
Sclk
D
M
FSELS
D
Pre_en
GND
FSELP
A
E_WR
A
M2_WR
A
Smode
A
Bmode
V
M1_WR
A_WR
F
F
GND
Name
in
in
5
6
7
0
1
2
3
DD
5
6
Pin
Serial,
Parallel
Serial
Parallel
Direct
Serial
Parallel
Direct
Serial
Parallel
Direct
ALL
Parallel
Direct
Serial
Parallel
Direct
Parallel
Direct
Serial,
Parallel
Direct
ALL
ALL
Parallel
Parallel
ALL
ALL
ALL
Interface
Mode
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
Input
Type
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk.
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for
programming of internal counters while in Serial Interface Mode.
Parallel data bus bit7 (MSB).
Prescaler enable, active “low”. When “high”, F
Ground.
Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for
programming of internal counters while in Parallel Interface Mode.
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into
the enhancement register on the rising edge of Sclk.
Enhancement register write. D[7:0] are latched into the enhancement register on the rising
edge of E_WR.
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of
M2_WR.
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode
(Bmode=0, Smode=0).
A Counter bit3 (MSB).
Selects direct interface mode (Bmode=1).
Same as pin 1.
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of
M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of
A_WR.
Hop write. The contents of the primary register are latched into the secondary register on the
rising edge of Hop_WR.
Prescaler input from the VCO. 3.0 GHz max frequency.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to
this pin and be connected in series with a 50 Ω resistor directly to the ground plane.
Ground.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Description
in
bypasses the prescaler.
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