ATA557001C-DDT Atmel, ATA557001C-DDT Datasheet - Page 7

• Manufacturer Part Number: ATA557001C-DDT
• Description: IC IDIC SENSOR RW 1KBIT UFBGA
• Manufacturer: Atmel
• Series: -r

Specifications of ATA557001C-DDT

• Function: Read/Write
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4. Operating the Atmel ATA5570C
4.1
4.2
4.3
9191B–RFID–05/11
Initialization and POR Delay
Tag-to-reader Communication
Regular-read Mode
The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold has
been reached. This in turn triggers the default start-up delay sequence. During this configura-
tion period of about 192 field clocks, the Atmel
data stored in EEPROM block 0. If the POR delay bit is reset, no additional delay is observed
after the configuration period. Tag modulation in regular-read mode will be observed about
3ms after entering the RF field. If the POR delay bit is set, the ATA5570C remains in a perma-
nent damping state until 8190 internal field clocks have elapsed.
T
Any field gap occurring during this initialization phase will restart the complete sequence. After
this initialization time the Atmel ATA5570C enters regular-read mode and modulation starts
automatically, using the parameters defined in the configuration register.
During normal operation, the data stored within the EEPROM is cycled and the COIL1 and
COIL2 terminals are load modulated. This resistive load modulation can be detected at the
reader module.
In regular-read mode, data from the memory is transmitted serially, starting with block 1, bit 1,
up to the last block (e.g., 7), bit 32. The last block which will be read is defined by the mode
parameter field MAXBLK in EEPROM block 0. When the data block addressed by MAXBLK
has been read, data transmission restarts with block 1, bit 1.
The user may limit the cyclic datastream in regular-read mode by setting the MAXBLK
between 0 and 7 (representing each of the 8 data blocks). If set to 7, blocks 1 through 7 can be
read. If set to 1, only block 1 is transmitted continuously. If set to 0, the contents of the config-
uration block (normally not transmitted) can be read. In the case of MAXBLK = 0 or 1,
regular-read mode can not be distinguished from block-read mode.
Figure 4-1.
Every time the Atmel
is a logical “0”. The data stream starts with block 1, bit 1, continues through MAXBLK, bit 32,
and cycles continuously if in regular-read mode.
This behavior is different from the original Atmel e555x and helps to decode PSK-modulated
data.
MAXBLK = 5
MAXBLK = 2
MAXBLK = 0
INIT
= (192 + 8190
Examples of Different MAXBLK Settings
Loading block 0
Loading block 0
Loading block 0
®
POR delay)
0
0
0
ATA5570C enters regular- or block-read mode, the first bit transmitted
Block 1
Block 1
Block 0
T
C
Block 4
Block 2
Block 0
67ms;
®
ATA5570C is initialized with the configuration
Block 5
Block 1
Block 0
T
C
= 8 µs at 125kHz
Atmel ATA5570C
Block 1
Block 2
Block 0
Block 2
Block 1
Block 0
7